Built-In Gate Driver Line Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
In flat panel display devices, the built-in gate driver experiences signal delay due to parasitic capacitance caused by the overlap of clock and power supply lines, leading to inefficiencies in pull-up signal transmission.
Innovation Solution
The configuration of the built-in gate driver includes clock and power supply lines disposed on opposite sides of the shift register, reducing overlap areas and parasitic capacitance, thereby enhancing the output characteristics of the pull-up signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If clock and power supply lines are disposed on one side of the shift register, then the device complexity is reduced, but signal delay increases due to parasitic capacitance from line overlap
Solution Approach 1:
The clock supply lines and power supply lines are segmented into two separate groups, with each group disposed on opposite sides of the shift register. This segmentation prevents the lines from overlapping, thereby reducing parasitic capacitance and signal delay while maintaining a relatively simple overall structure.
Solution Approach 2:
The line arrangement transitions from a one-sided concentrated layout to a two-sided distributed layout. By utilizing both sides of the shift register for line placement, the design reduces line overlap in the vertical dimension while distributing lines across the horizontal dimension, effectively reducing parasitic capacitance.
2Area of stationary object
If clock and power supply lines overlap, then the area utilization is improved, but parasitic capacitance increases causing signal degradation
Solution Approach 1:
The harmful overlap between clock and power supply lines is extracted and eliminated by disposing the lines on opposite sides of the shift register. This separation removes the source of parasitic capacitance generation while maintaining efficient area utilization through compact line routing.
3Object-generated harmful factors
If lines are disposed on opposite sides of the shift register, then parasitic capacitance is reduced, but the line length increases
Solution Approach 1:
The line arrangement optimizes local quality by placing clock and power supply lines on opposite sides where they are least likely to overlap with signal lines. This localized separation reduces parasitic capacitance at critical overlap points, compensating for the increased line length through improved signal integrity in key areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces signal delay and improves the performance of the built-in gate driver and the overall flat panel display device by minimizing the overlap between clock and power supply lines.
Implementation Method 1
signal delay due to parasitic capacitance caused by the overlap of clock and power supply lines
Data Source
AI summary
A built-in gate driver includes a shift register provided in a non-display area of a panel, and configured to include first to gth stages outputting a scan signal, a clock supply line part configured to include m number of clock supply lines connected to the shift register, and a power supply line part configured to include n number of power supply lines connected to the shift register. At least one of the lines of the clock supply lines and the power supply lines are in a first side direction of the shift register, and the other at least one or more lines of the clock supply lines and the power supply lines are in a second side direction of the shift register.