Gate Driver Circuit for Stable Low-Frame-Rate Gate Output

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Solution Overview

Problem

Conventional gate drivers experience instability in outputting gate signals, particularly in low frame rate modes due to leakage currents and inaccurate voltage levels.

Innovation Solution

The gate driver incorporates N-type transistors, specifically a pull-down transistor, to stabilize gate output signals by maintaining a consistent voltage level independent of the transistor's threshold voltage, using a 6T1C circuit structure with distinct channel width-to-length ratios and additional transistors to manage power voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a conventional gate driver uses a pull-down transistor with P-type characteristics, then the circuit structure is simple, but the gate output signal voltage becomes inaccurate due to threshold voltage differences and leakage currents

Engineering Contradiction:
Improvegate output signal voltage accuracyVSAvoidcircuit structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent changes the transistor type parameter from P-type to N-type for the pull-down transistor. This parameter change eliminates the threshold voltage offset issue because N-type transistors have lower threshold voltages and smaller leakage currents, thereby improving gate output signal voltage accuracy without significantly increasing circuit complexity

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent substitutes the conventional P-type transistor mechanism with an N-type transistor mechanism. This substitution replaces the voltage-dependent threshold voltage mechanism with a lower threshold voltage mechanism that reduces leakage current effects, achieving more accurate voltage output

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If the gate driver operates in low frame rate mode, then power consumption is reduced, but leakage currents cause instability in gate output signals

Engineering Contradiction:
Improvegate output signal stabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent converts the harmful leakage current effect into a beneficial outcome by using N-type transistors with inherently lower leakage currents. The lower leakage current characteristic of N-type transistors becomes advantageous in low frame rate operation, maintaining signal stability while reducing power consumption

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent changes the transistor type parameter to N-type, which fundamentally alters the leakage current characteristic. This parameter change reduces the leakage current magnitude, making the gate driver more reliable in low frame rate modes where leakage currents would otherwise cause significant instability

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12512039B2Gate driver and display apparatus including the same
Publication Date: 2025.12.30 SAMSUNG DISPLAY CO LTD
  • US12512039B2 patent drawing
  • US12512039B2 patent drawing
  • US12512039B2 patent drawing

AI summary

A gate driver includes a first transistor including a control electrode, a first electrode receiving a previous signal and a second electrode electrically connected to a Q node, a second transistor including a control electrode electrically connected to the Q node, a first electrode receiving a first voltage and a second electrode electrically connected to a QB node, a third transistor including a control electrode electrically connected to the Q node, a first electrode electrically connected to the QB node and a second electrode receiving a second voltage, a fourth transistor including a control electrode electrically connected to the QB node, a first electrode receiving the first voltage and a second electrode electrically connected to a GO node and a fifth transistor including a control electrode electrically connected to the Q node, a first electrode electrically connected to the GO node and a second electrode receiving the second voltage.