Gate Driver Stage Circuit for Stable Low-Level Scan Signals
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Solution Overview
Problem
In display devices, the generation of output signals (such as scan and emission control signals) is affected by repeated charging and discharging of capacitors when the signals are at a low level, leading to current generation that impacts transition time and waveform of clock signals, causing power consumption and impedance changes.
Innovation Solution
A gate driver design with a first stage outputting an inverted carry signal using a start pulse and a second stage outputting a gate signal based on a carry signal, incorporating input circuits, output circuits, control circuits, and stabilizing circuits to maintain stable node voltages and prevent undesired charge/discharge operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a stage outputs a low-level signal and capacitors are repeatedly charged/discharged by clock signals, then the clock signal can drive the stage, but current is generated that affects transition time and waveform of the clock signal, causing power consumption and impedance changes
Solution Approach 1:
The patent extracts and removes the capacitor from the circuit during periods when the output signal is at a low level. By disconnecting the capacitor that would otherwise be repeatedly charged and discharged by the clock signal, the source of harmful current is eliminated, thereby reducing power consumption and preventing impedance changes while maintaining signal transition speed.
Solution Approach 2:
The patent applies preliminary anti-action by proactively controlling the capacitor's connection state before the harmful charge/discharge cycle begins. The control circuit preemptively disconnects the capacitor when the output signal goes low, preventing the generation of harmful current that would affect clock signal waveform and increase power consumption.
2Stability of the object's composition
If capacitors are repeatedly charged/discharged by clock signals, then the stage can maintain signal levels, but current generation impacts waveform and transition time of clock signals
Solution Approach 1:
The patent applies dynamics by making the capacitor's connection state variable rather than fixed. The capacitor is dynamically connected during periods when signal stability is needed and disconnected when it would harm transition speed. This time-varying configuration allows the system to optimize between stability and speed at different operational moments.
Solution Approach 2:
The patent implements periodic action by rhythmically connecting and disconnecting the capacitor based on the output signal level. The capacitor is connected during high-level output periods for stability and disconnected during low-level periods to prevent harmful current flow, creating a periodic on/off pattern that balances stability and transition speed requirements.
3Use of energy by moving object
If the output signal is at a low level, then power consumption is reduced, but capacitors are repeatedly charged/discharged causing impedance changes and waveform distortion
Solution Approach 1:
The patent extracts the capacitor from the active circuit during low-level output periods, removing it from positions where it would cause harmful charge/discharge cycles. This extraction eliminates the source of impedance changes and waveform distortion while maintaining the low power consumption state.
Solution Approach 2:
The patent introduces a control circuit as an intermediary between the clock signal source and the capacitor. This intermediary component intelligently manages the capacitor's connection state, preventing direct interaction between the clock signal and capacitor during low-level output periods, thereby blocking the harmful current path that would cause impedance changes.
Data Source
AI summary
A gate driver includes first and second stages. Each of the first and second stages includes an output circuit which outputs a scan signal, a carry signal and an inverted carry signal based on voltages of first and second nodes, a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal. The first stage further includes a first input circuit which controls the voltages of the first and second nodes thereof based on a start pulse and a signal supplied to the second input terminal. The second stage further includes a second input circuit which controls the voltages of the first and second nodes thereof based on a first carry signal and a first inverted carry signal, and a signal supplied to the second input terminal. The second stage is dependently connected to the first stage.