Multi-Stage Gate Driver Circuit for Lower Power and Dead Space
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Solution Overview
Problem
The increasing number of configurations in gate drivers leads to higher power consumption and larger dead spaces in display devices.
Innovation Solution
A gate driver design incorporating a plurality of stages with input circuits, inversion control circuits, and gate output circuits, utilizing PMOS transistors and capacitors, operates efficiently with two clock signals to reduce power consumption and dead space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of configurations (transistors, signal lines, voltage lines) in the gate driver is increased, then the functionality and control capability are improved, but the power consumption increases and the dead space becomes larger
Solution Approach 1:
The gate driver is divided into multiple stages, with each stage independently driving one gate line. Each stage includes dedicated transistors (first to fifth transistors) and capacitors (first and second capacitors) that are activated only when needed for specific gate signal generation, reducing overall power consumption while maintaining full control capability across all gate lines
Solution Approach 2:
The gate driver uses clock signals (first clock signal and second clock signal) to periodically control the switching of transistors in each stage. This periodic switching enables precise timing control of gate signals while minimizing the duration that transistors remain conductive, thereby reducing power consumption during non-active periods
2Adaptability or versatility
If the number of configurations (transistors, signal lines, voltage lines) in the gate driver is increased, then the functionality and control capability are improved, but the dead space becomes larger
Solution Approach 1:
Each stage is configured as an independent module with dedicated transistors and capacitors, allowing the driver to activate only the necessary components for current operation. This modular segmentation reduces the simultaneous occupancy of signal lines and transistor gates, minimizing dead space while preserving full adaptability
Solution Approach 2:
The transistors and capacitors in each stage serve multiple functions: the first transistor controls input signal transmission, the second and third transistors manage capacitor charging/discharging, the fourth transistor controls output, and the fifth transistor provides clock signal gating. This multi-functionality reduces the total number of dedicated components needed, thereby reducing dead space
3Reliability
If more transistors and circuit components are added to the gate driver stages, then the signal control precision and gate signal quality are improved, but the power consumption and device complexity increase
Solution Approach 1:
The gate driver is segmented into identical reusable stages, each containing a standardized set of five transistors and two capacitors. This segmentation allows complex signal control functionality to be achieved through repetition of simple, well-defined modules, improving gate signal quality while making the overall device complexity manageable through modularity
Solution Approach 2:
The invention optimizes the electrical parameters of the transistor-capsitor network to achieve reliable gate signal generation. By carefully selecting transistor sizes, threshold voltages, and capacitor values, the circuit achieves high signal quality with a minimal number of components, avoiding unnecessary complexity
Data Source
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AI summary
A gate driver includes a plurality of stages. Each of the plurality of stages includes an input circuit configured to provide an input signal to a control node in response to a first clock signal, a first inversion control circuit configured to control a voltage of an inversion control node in response to a voltage of the control node, and a gate output circuit configured to output a gate signal in response to the voltage of the control node and the voltage of the inversion control node.