Gate Driver Multi-Clock Pulse Signal Compensation
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Solution Overview
Problem
Existing organic light emitting display devices face challenges in accurately compensating the threshold voltage of driving transistors due to hysteresis characteristics, leading to delays and increased loads in gate signals, which degrade display quality.
Innovation Solution
A gate driver is designed with clock signal lines transferring multiple clock signals, where adjacent gate driving units receive the same but independent clock signals, generating gate signals with multi-clock pulses to reduce signal loads and delays, thereby compensating the threshold voltage effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a certain voltage is repeatedly applied to compensate threshold voltage based on gate signal, then accuracy of threshold voltage compensation is improved, but load of gate signal increases and gate signal is delayed
Solution Approach 1:
The gate driver is divided into multiple gate driving units (first, second, third, etc.) that operate independently and sequentially. Each gate driving unit generates gate signals for different gate lines, allowing the compensation voltage to be applied to different segments of the display simultaneously rather than sequentially to the entire display, thereby reducing overall gate signal delay while maintaining compensation accuracy.
Solution Approach 2:
The gate driver uses clock signals with different phases to control the periodic operation of multiple gate driving units. By utilizing multi-phase clock signals, the system can apply compensation voltages in a periodic manner across different gate lines, ensuring accurate threshold voltage compensation while distributing the timing load to reduce signal delay.
2Loss of time
If multiple clock signals are used to generate gate signals for multiple gate driving units, then gate signal load and delay are reduced, but device complexity increases
Solution Approach 1:
Multiple clock signal lines are generated with different phases but follow the same basic waveform pattern. These multi-phase clock signals serve universal functions by controlling different gate driving units in a standardized manner, reducing the need for separate control circuits for each gate line while still achieving reduced signal delay through parallel operation.
Solution Approach 2:
The use of periodic clock signals with different phases allows the gate driver to maintain a regular, predictable operation pattern. This periodic structure simplifies the control logic compared to arbitrary timing schemes, as each gate driving unit follows the same rhythmic pattern shifted in phase, reducing overall system complexity while enabling faster operation.
Data Source
AI summary
A gate driver includes clock signal lines respectively transferring clock signals, at least two of the clock signals being mutually the same; and gate driving units electrically connected to the clock signal lines, respectively and configured to sequentially generate gate signals having a multi-clock pulse based on the clock signals.