Gate Driver Circuit Layout for Narrow-Bezel Display Panels
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Solution Overview
Problem
Current gate driver circuits in flat panel displays, such as liquid crystal display devices, face challenges in downsizing and reducing the bezel width due to the large size of shift register units, which also lead to increased signal delay times.
Innovation Solution
The proposed solution involves a driver circuit design that includes a shift register unit and a demultiplexer circuit connected to multiple signal lines, allowing for a reduced width of the shift register unit without increasing signal delay, achieved by optimizing the connection and configuration of transistors and buffers within the circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the shift register unit is made larger to accommodate more circuits, then the circuit functionality is improved, but the width of the gate driver circuit increases and signal delay time increases
Solution Approach 1:
The gate driver circuit is divided into multiple stages, with each stage containing a shift register unit and a demultiplexer circuit. The demultiplexer circuit segments the signal lines to distribute signals to different output lines, allowing the circuit to handle more signal lines without proportionally increasing the width of each shift register unit.
Solution Approach 2:
The circuit architecture transitions from a planar expansion to a multi-layer signal distribution approach. By introducing the demultiplexer circuit that distributes signals across multiple output lines, the system achieves increased functionality without linearly increasing the horizontal width of the gate driver circuit.
2Loss of time
If the shift register unit is made larger to reduce signal delay, then the signal delay time is improved, but the width of the gate driver circuit increases
Solution Approach 1:
The signal path is segmented through the demultiplexer circuit, which distributes signals to multiple output lines. This segmentation allows for optimized signal routing that reduces delay time without requiring a larger shift register unit width.
Solution Approach 2:
The demultiplexer circuit acts as an intermediary between the shift register unit and the output signal lines. It receives signals from the shift register and distributes them to multiple output lines, enabling efficient signal distribution that reduces delay without increasing the shift register unit width.
3Adaptability or versatility
If the demultiplexer circuit is connected to more signal lines, then the circuit versatility is improved, but the device complexity increases
Solution Approach 1:
The demultiplexer circuit is designed to handle multiple signal lines with a standardized architecture. Each demultiplexer unit can distribute signals to multiple output lines, providing universal functionality that increases circuit versatility without requiring separate complex circuits for each signal line.
Data Source
AI summary
To provide a semiconductor device including a narrowed bezel obtained by designing a gate driver circuit. A gate driver of a display device includes a shift register unit, a demultiplexer circuit, and n signal lines. By connecting the n signal lines for transmitting clock signals to one stage of the shift register unit, (n−3) output signals can be output. The larger n becomes, the smaller the rate of signal lines for transmitting clock signals which do not contribute to output becomes; accordingly, the area of the shift register unit part is small compared to a conventional structure in which one stage of a shift register unit outputs one output signal. Therefore, the gate driver circuit can have a narrow bezel.