Gate Driver Transistor Layout for Narrow-Bezel Display Panels
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Solution Overview
Problem
Current display devices face challenges in reducing the dead space area while improving the current driving capability of pull-up and pull-down transistors, which affects the overall efficiency and design of the display panel.
Innovation Solution
The implementation of a display device design where pull-up and pull-down transistors include multiple sub-transistors connected in parallel, sharing at least one gate electrode, which enhances current driving ability and reduces transistor size, thereby minimizing the gate driving circuit's area and the associated dead space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of transistors in the gate driving circuit is increased to improve current driving capability, then the current driving ability is improved, but the area of the non-display area increases
Solution Approach 1:
Multiple sub-transistors (first sub-transistor and second sub-transistor) are combined into a single pull-up transistor structure, where they share common gate electrodes and source/drain electrodes. This merging allows the transistors to operate in parallel, improving current driving capability while reducing the overall area occupied compared to using separate independent transistors.
Solution Approach 2:
The shared gate electrodes and source/drain electrodes serve multiple functions simultaneously. The first and second gate electrodes collectively control both sub-transistors, and the shared source/drain electrodes provide electrical connections for both transistors, reducing the total number of components needed and minimizing the non-display area.
2Area of stationary object
If the transistor size is reduced to minimize dead space area, then the non-display area is reduced, but the current driving capability deteriorates
Solution Approach 1:
The pull-up transistor is segmented into multiple sub-transistors (first sub-transistor and second sub-transistor) that operate in parallel. Each sub-transistor can be designed with optimized dimensions, and their combined effect provides sufficient current driving capability even when individual transistor sizes are reduced to minimize dead space area.
3Power
If multiple sub-transistors are used to improve current driving ability, then the current driving capability is improved, but the device complexity increases
Solution Approach 1:
Multiple sub-transistors are merged into a unified structure by sharing gate electrodes and source/drain electrodes. This merging reduces the total number of discrete components and interconnections needed, thereby reducing device complexity while maintaining the current driving benefits of having multiple parallel transistor channels.
Data Source
AI summary
The disclosure relates to a display device, and more particularly, to a display device capable of reducing a dead space area while improving current driving capability of pull-up and pull-down transistors. According to an embodiment of the disclosure, a substrate having a display area and a non-display area; pixels arranged in the display area of the substrate; and a gate driving circuit disposed in the non-display area of the substrate and connected to a transistor of the pixel. The gate driving circuit includes a pull-up transistor and a pull-down transistor. At least one of the pull-up and pull-down transistors includes a plurality of sub-transistors including a plurality of gate electrodes, and wherein the sub-transistors shares at least one of the gate electrodes.