Gate Driver Negative Bias Switching Against False Turn-On

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Solution Overview

Problem

Existing gate driving circuits face issues with erroneous turning-on of transistors due to parasitic inductance and capacitance, leading to increased power loss and through currents, which are not adequately addressed by current mirror clamp functions.

Innovation Solution

Incorporation of bias switchers in the gate driving circuit to dynamically control the gate-source voltage of transistors using negative biasing and delayed switching, preventing erroneous turning-on by maintaining the voltage within safe thresholds and reducing power loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a mirror clamp function is used to prevent erroneous turning-on, then transistor reliability is improved, but power loss increases due to through currents

Engineering Contradiction:
Improvetransistor reliabilityVSAvoidpower loss
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The bias switcher is activated before the main switching operation to pre-establish the negative bias voltage on the gate-source terminal. This preliminary action ensures that when through currents occur during switching, the transistor remains biased in a safe state that prevents erroneous turning-on, thereby maintaining reliability while reducing the magnitude of harmful currents.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention dynamically changes the gate-source voltage parameter by applying a negative bias voltage during switching transitions. This parameter change shifts the operating point of the transistor to a region where it is less susceptible to erroneous turning-on from parasitic inductance and capacitance effects, thus improving reliability while controlling power loss.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If mirror clamp transistors are used to clamp gate voltage, then erroneous turning-on is prevented, but device complexity increases

Engineering Contradiction:
Improveerroneous turning-on preventionVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The bias switcher circuit performs multiple functions: it provides negative biasing during switching transitions, clamps the gate-source voltage to prevent erroneous turning-on, and reduces power loss from through currents. By consolidating these functions into a single circuit block rather than using separate mirror clamp transistors, the invention reduces device complexity while maintaining reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If negative biasing is applied continuously to prevent erroneous turning-on, then transistor reliability is improved, but power consumption increases

Engineering Contradiction:
Improvetransistor reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The bias switcher activates negative biasing only during specific periods when switching transitions occur or when there is a risk of erroneous turning-on. During normal steady-state operation, the negative bias is removed or reduced, allowing the transistor to operate with minimal power consumption while maintaining reliability during critical transition periods.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS12431896B2Gate driving circuit
Publication Date: 2025.09.30 ROHM CO LTD
  • US12431896B2 patent drawing
  • US12431896B2 patent drawing
  • US12431896B2 patent drawing

AI summary

A gate driving circuit (10X) is configured to be capable of driving a driving target transistor (QH) having a gate and a first terminal, and includes: an application terminal to which a negative voltage (VEE1) is applied; a driving transistor (MOS1) that has a control terminal fed with a control signal (MC1) and that is connected between the gate of the driving target transistor and the application terminal; and a bias switcher (101B) configured to feed the first terminal of the driving target transistor with either a ground potential (GND1) or the negative voltage selectively according to the logic level of the control signal at a timing delayed from the timing at which the control signal switches its logic level.