Gate Driver Node Control for Stable Short-Pulse Scanning
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Solution Overview
Problem
Existing display devices face challenges in efficiently driving n-type transistors and maintaining stable scan signal output, often requiring separate power lines that increase bezel area and power consumption.
Innovation Solution
A gate driver design that includes a node controller and scan signal output unit, utilizing clock signals to control voltages at multiple nodes and determine scan signal width, allowing for pulse widths of 1 H or less, and eliminating the need for a separate power line for inverters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate power line is used for driving the inverter, then the inverter can be driven stably, but the bezel area increases and power consumption increases
Solution Approach 1:
The patent merges the power supply function for the inverter into the existing gate driver circuit by utilizing the Q node and QB node voltage control mechanisms. The inverter is driven using voltages already present in the gate driver's operational nodes, eliminating the need for a separate dedicated power line and reducing bezel area while maintaining driving stability.
Solution Approach 2:
The gate driver circuit is designed to perform multiple functions: it controls the scan signal output and simultaneously provides the necessary power supply for the inverter through its Q node and QB node voltage swings. This multi-functional design eliminates redundant power lines and reduces overall circuit complexity.
2Reliability
If a separate power line is used for driving the inverter, then the inverter can be driven stably, but the power consumption increases
Solution Approach 1:
The power supply for the inverter is combined with the gate driver's existing voltage control nodes (Q node and QB node). By reusing the voltage swings already present in these nodes for both scan signal generation and inverter power supply, the patent eliminates redundant power consumption associated with separate power lines while maintaining stable inverter operation.
3Adaptability or versatility
If the scan signal width is reduced to 1 H or shorter, then the driving timing can be adjusted flexibly, but the transistor switching speed requirements increase
Solution Approach 1:
The patent utilizes parameter changes in the voltage levels at the Q node and QB node to achieve fast switching. By controlling the voltage transitions at these nodes through clock signals and carry signals, the circuit can generate scan signals with pulse widths of 1 H or shorter, providing flexible driving timing while meeting the speed requirements through voltage-level optimization rather than purely relying on transistor speed.
Data Source
AI summary
The present disclosure relates to gate driver and display device including the same. According to an aspect of the present disclosure, a gate driver includes: a plurality of stages which is dependently connected to each other, each of the plurality of stages includes: a node controller configured to control voltages of a Q node, a Q1 node, a Q2 node, a QB node, a QB1 node, and a QB2 node based on a first clock signal and a second clock signal; a carry signal output unit configured to output a carry signal to a next stage based on the voltages of the Q1 node and the QB1 node; and a scan signal output unit configured to output a scan signal to a scan line based on the voltages of the Q node and the QB node, and a width of the scan signal may be determined by a toggling timing of the first clock signal and a toggling timing of the second clock signal.