Gate Driver Noise Removal for Stable Pull-Up Node Discharge

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Solution Overview

Problem

Existing gate drivers in display devices face issues with abnormal output of gate-high voltage due to negatively shifted threshold voltage of transistors, leading to leakage currents and noise, which affect the stability of pull-up node discharge potential.

Innovation Solution

A gate driver design that includes noise removing units with multiple transistors to manage the pull-up and pull-down nodes, ensuring stable discharge potential by using transistors responsive to specific gate-on and clock signals, and a pull-up node reset unit to maintain the discharge potential.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single noise removing transistor is used to remove noise from the pull-up node, then the device complexity is reduced, but the reliability deteriorates due to threshold voltage shifts causing leakage current and abnormal gate-high voltage output

Engineering Contradiction:
Improvenoise removing unit structureVSAvoidgate-high voltage output stability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The noise removing function is segmented into multiple transistors (first noise removing transistor T1 and second noise removing transistor T2) that operate independently but complementarily. Each transistor handles different aspects of noise removal, and the segmentation allows the system to maintain reliability even if one transistor's threshold voltage shifts, as the other can compensate for the leakage current.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If transistors are used without threshold voltage compensation, then the manufacturing precision requirements are reduced, but the stability of pull-up node discharge potential deteriorates due to negatively shifted threshold voltage

Engineering Contradiction:
Improvetransistor threshold voltage controlVSAvoidpull-up node discharge potential
Core Design Contradiction:
Manufacturing precisionVSStability of the object's composition

Solution Approach 1:

The system changes the operational parameters of the transistors by applying different gate voltages (first gate voltage to T1, second gate voltage to T2) and utilizing different clock signal phases. This parameter differentiation allows the transistors to operate in different regions, compensating for threshold voltage shifts and maintaining stable discharge potential without requiring extremely tight manufacturing precision.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If multiple noise removing transistors are used to compensate for threshold voltage shifts, then the reliability is improved, but the device complexity increases

Engineering Contradiction:
Improvenoise removal effectivenessVSAvoidnumber of transistors in noise removing unit
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple noise removing transistors are merged into a single integrated noise removing unit that shares common circuit elements such as the pull-up node connection point and clock signal input. The transistors are combined in parallel configuration where their collective function achieves reliable noise removal without requiring separate independent circuits for each transistor, thus limiting the increase in overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP3035325B1Gate driver and display device including the same
Publication Date: 2019.12.04 LG DISPLAY CO LTD
  • EP3035325B1 patent drawingFigure 1~2
  • EP3035325B1 patent drawingFigure 3~4
  • EP3035325B1 patent drawingFigure 5A~5B

AI summary

A gate driver and a display device including the gate driver are provided which can prevent an abnormal output of a gate-high voltage from a stage by stably maintaining a discharge potential of a pull-up node (NQ). The gate driver includes a plurality of stages (STAq), and each stage (STAq) includes a pull-up transistor (TU), a pull-down transistor (TD), and a first noise removing unit (100). The pull-up transistor outputs a first clock signal, which is input to a first clock terminal (CT1), to an output terminal (OT) depending on a voltage of a pull-up node (NQ). Conversely the pull-down transistor (TD) outputs a first source voltage, input to a first source voltage terminal (VSST), to the output terminal (OT) depending on a voltage of a pull-down node (NQB) resulting from a second clcock signal which is input to a second clock terminal (CT3). The first noise removing unit (100) has a first transistor (T1) which supplies the first source voltage as a gate-off voltage to the pull-up node (NQ), in response to the clock signal input to the first clock terminal (CT1), to remove noise of the pull-up node (NQ).