Gate Driver Noise Suppression Using Cascaded Inverters

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Solution Overview

Problem

Conventional monolithically integrated gate drivers in display devices suffer from noise issues due to temperature-dependent semiconductor characteristics, leading to undesirable waveform distortions in gate drive voltage signals, especially at higher temperatures.

Innovation Solution

The implementation of gate line pull-down circuits controlled by an A-node, utilizing a cascaded chain of stages with first and second inverters synchronized with different clock signals to suppress noise and maintain a predetermined waveform, ensuring the gate lines remain noise-free except during brief periods when necessary, and using a transfer signal generating unit to manage voltage levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a monolithically integrated gate driver is implemented on the TFT array substrate, then manufacturing cost is reduced and device reliability is improved, but noise interference occurs in gate lines at higher temperatures due to temperature-dependent semiconductor characteristics

Engineering Contradiction:
Improvedevice reliabilityVSAvoidnoise interference
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The gate driver circuit is divided into multiple independent stages (first stage, second stage, third stage, etc.), where each stage consists of separate pull-up and pull-down circuits. This segmentation allows independent control of each stage's output, enabling precise management of noise interference while maintaining the monolithic integration benefits.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different stages of the gate driver are assigned different control strategies based on their specific operational requirements. The pull-down circuits in each stage are controlled by distinct control signals (first control signal, second control signal, third control signal, etc.), allowing localized optimization of noise suppression in each region of the circuit.

Inventive Principle:
Principle #3Local quality

2Temperature

If the gate driver operates at higher temperatures, then display device performance is maintained, but waveform distortion and noise spikes increase due to changes in amorphous semiconductor material characteristics

Engineering Contradiction:
Improveoperating temperatureVSAvoidwaveform accuracy
Core Design Contradiction:
TemperatureVSManufacturing precision

Solution Approach 1:

The pull-down circuits are activated in advance to counteract the noise and waveform distortion that would otherwise occur at higher temperatures. By preemptively controlling the gate line voltage levels through the pull-down circuits, the system prevents noise spikes before they can corrupt the gate drive voltage waveform.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The gate driver circuit incorporates control mechanisms that respond to temperature-induced changes in semiconductor characteristics. The control signals for the pull-down circuits are designed to compensate for temperature effects, maintaining waveform accuracy despite thermal variations in the amorphous semiconductor material.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8723844B2Display panel
Publication Date: 2014.05.13 SAMSUNG DISPLAY CO LTD
  • US8723844B2 patent drawing
  • US8723844B2 patent drawing
  • US8723844B2 patent drawing

AI summary

Noise is reduced at a so-called Q-node and a so-called A-node of shift registers in a gate lines driving block of a scan driven display system so that the display system can be safely operated even at elevated temperatures. A variety of techniques may be used to reduce the noise. A first of the techniques applies charging pulses to the A-node at a rate faster than just once every 2H durations, where 1H is the duration of a single row drive. More specifically, a plurality of so-called inverter circuits, rather than just one are included in each shift register stage and the inverters are operated in synchronism with out of phase clock signals so as to thereby increase the rate at which the A-node is pulsed to a high voltage level. A second technique charges up the Q-node in multiple steps. A third technique pulls down the carry line at times when it does not need to go high. A fourth technique combines one or more of the first through third techniques.