Gate Driver Circuit for Narrow Bezel OLED Displays
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Solution Overview
Problem
Existing organic light-emitting display devices face challenges in achieving a narrow bezel and real-time sensing of driving characteristic variations, which are essential for enhancing display efficiency and user experience.
Innovation Solution
A gate driver with multiple stages, each comprising a first pull-up transistor for outputting a carry clock, a second pull-up transistor for outputting a scan clock, and holding transistors that operate based on a QB node voltage, which is charged and discharged reversely to the Q node, and are electrically isolated from the first output terminal, allowing for simplified circuit configuration and real-time sensing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a gate driver is included in a non-display area (bezel area) of a display panel, then the gate driver can be integrated into the display device, but the bezel area increases which reduces the display surface area
Solution Approach 1:
The holding transistors are extracted from the carry output terminal, removing them from the critical path of the gate driver circuit. This extraction allows the gate driver to be positioned in the bezel area while minimizing the bezel width, as the holding transistors no longer contribute to the circuit area at the output terminal.
Solution Approach 2:
The gate driver circuit is segmented into functional blocks: pull-up transistors for signal generation, holding transistors for voltage maintenance, and electrically isolated sections for signal output. This segmentation allows optimization of each component's placement to minimize overall bezel area while maintaining functionality.
2Area of stationary object
If the gate driver circuit is simplified to reduce bezel area, then the bezel width decreases, but the circuit complexity may be reduced which could affect functionality
Solution Approach 1:
Holding transistors are extracted from the carry output terminal, simplifying the circuit configuration at critical nodes. This extraction reduces the number of components that need to be positioned and connected in the bezel area, thereby reducing bezel width without compromising the gate driver's functional complexity.
Solution Approach 2:
Multiple functions are merged into the pull-up transistors which simultaneously generate carry signals and scan signals through coordinated operation with the holding transistors. This merging reduces the total component count and simplifies the circuit architecture while maintaining full functionality.
3Stability of the object's composition
If holding transistors are connected to both first and second output terminals, then signal stability is improved, but the circuit complexity and bezel area increase
Solution Approach 1:
Holding transistors are extracted from the carry output terminal connection, eliminating the need for them to be connected to both output terminals. This extraction maintains signal stability at the scan output terminal while simplifying the overall circuit configuration and reducing bezel area requirements.
Solution Approach 2:
The circuit is segmented such that holding transistors are electrically isolated from the first output terminal (carry signal) while remaining connected to the second output terminal (scan signal). This segmentation allows independent optimization of signal stability for each output path without increasing overall circuit complexity.
Data Source
AI summary
The present disclosure relates to a gate driver and an organic light-emitting display device including same. A gate driver according to an embodiment of the present disclosure includes a plurality of stages. Each of the stages includes: a first pull-up transistor configured to output a carry clock to a first output terminal as a carry signal while a Q node is bootstrapped to a voltage higher than a gate on voltage; a second pull-up transistor configured to output a scan clock to a second output terminal as a scan signal while the Q node is bootstrapped; and holding transistors configured to operate based on a voltage of a QB node, which QB node is charged and discharged in a manner reverse to that of the Q node. The holding transistors are connected to the second output terminal and the Q node, and the holding transistors are electrically isolated from the first output terminal.