Gate Driver Fault Detection via Parasitic Capacitors
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Solution Overview
Problem
Existing power transistor switch systems face challenges in detecting fault conditions, such as short circuits, during hard-switching and soft-switching modes, with traditional DESAT-based gate drivers requiring extraneous circuitry and increased footprint, necessitating a more efficient failure detection mechanism.
Innovation Solution
A gate driver system with a gate sense pin and circuit that includes an overcurrent detection circuit for soft-switching mode and a Miller plateau detection circuit for hard-switching mode, using parasitic capacitors to monitor voltage and current at the transistor gate, enabling timely fault detection and prevention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional DESAT-based gate drivers are used to detect fault conditions, then fault detection capability is provided, but the device footprint increases due to required extraneous circuitry
Solution Approach 1:
The patent merges the fault detection function with the existing gate driver circuit by utilizing the parasitic capacitors (Cge and Cgc) that are inherently present in the transistor-gate driver interface. The gate sense pin is integrated into the gate driver package, eliminating the need for separate external sensing circuits and reducing overall footprint while maintaining fault detection capability.
Solution Approach 2:
The invention leverages the self-existing parasitic capacitors of the transistor as the sensing element for fault detection. Instead of requiring external sensing components, the system uses the inherent electrical characteristics of the transistor-gate interface to detect fault conditions, thereby eliminating extraneous circuitry.
2Device complexity
If a gate sense pin is integrated into the gate driver to reduce footprint, then device complexity is reduced, but the difficulty of detecting and measuring fault conditions increases
Solution Approach 1:
The gate sense pin provides direct feedback from the gate terminal to the gate driver internal circuitry. The control logic circuit continuously monitors the voltage at the gate terminal through the integrated sense pin, enabling real-time detection of fault conditions such as short circuits between gate and emitter or gate and collector, thereby simplifying the detection process despite the integrated structure.
Solution Approach 2:
The gate sense pin acts as an intermediary element that bridges the gate terminal and the internal control logic circuit. It provides a direct electrical pathway for monitoring gate voltage without requiring external sensing components, thus maintaining ease of detection while achieving circuit integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively identifies and responds to fault conditions within microseconds, enhancing transistor reliability and reducing the overall footprint of the gate drive circuit, thereby improving power transistor switch operation in inverter applications.
Implementation Method 1
the transistor comprises a first parasitic capacitor between the gate and the emitter terminals and a second parasitic capacitor between the gate and the collector terminals
Data Source
AI summary
In some examples, a gate driver includes a gate sense pin and a gate sense circuit configured to couple to a node of a transistor via the gate sense pin. The gate sense circuit includes an overcurrent detection circuit configured to detect a first fault condition based on the node before the transistor turns on in a soft switching mode. The gate sense circuit also includes a Miller plateau detection circuit configured to detect a second fault condition based on the node when the transistor is turning on in a hard switching mode.