Half-Bridge Gate Driver Phase-Node Fault Detection for Inverter Protection

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Solution Overview

Problem

Existing power inverter systems lack effective protection mechanisms for new generations of power transistors with reduced short circuit capability and smaller thermal mass, particularly in low-power applications, making them vulnerable to fault operating conditions.

Innovation Solution

A monolithic half-bridge gate driver integrates fault detection circuitry onto the gate driver, monitoring phase node voltages and comparing them with thresholds to detect fault conditions, such as low-side desaturation, phase node-to-ground shorts, and high-side desaturation, using a compact 8-pin package.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If fault detection circuitry is integrated onto the gate driver, then protection capability is improved, but device complexity increases

Engineering Contradiction:
Improveprotection capabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent integrates fault detection circuitry (comparators, diodes, inverter) directly onto the gate driver chip, merging previously separate protection functions with the main gate driver functionality. This consolidation improves reliability by ensuring protection is always present while managing complexity through integrated circuit design techniques.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If fault detection circuitry is integrated onto the gate driver, then protection capability is improved, but package size increases

Engineering Contradiction:
Improveprotection capabilityVSAvoidpackage size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

By merging the fault detection circuitry with the gate driver onto a single integrated circuit chip, the patent avoids the need for separate discrete protection components. This integration achieves comprehensive protection capability while maintaining a compact 8-pin package size, as the entire protection functionality is embedded within the gate driver itself.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If fault detection circuitry is integrated onto the gate driver, then protection capability is improved, but manufacturing cost increases

Engineering Contradiction:
Improveprotection capabilityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The integration of fault detection circuitry onto the gate driver chip reduces the total component count and assembly steps required. Although the integrated circuit itself may have higher unit cost, the overall manufacturing cost decreases due to eliminated separate protection components, reduced PCB real estate, and simplified assembly processes.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The gate driver is designed to perform multiple functions: normal gate driving functionality plus integrated fault detection for desaturation, phase node-to-ground shorts, and high-side desaturation. This multi-functionality eliminates the need for separate protection circuits, reducing overall system complexity and manufacturing costs despite the enhanced protection capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12368374B2Protecting a power inverter by sensing a phase node voltage
Publication Date: 2025.07.22 INFINEON TECH AUSTRIA AG
  • US12368374B2 patent drawing
  • US12368374B2 patent drawing
  • US12368374B2 patent drawing

AI summary

A monolithic half-bridge gate driver includes a phase node terminal configured to be coupled to a phase node to which a high-side transistor and a low-side transistor of a half-bridge are coupled; a diode comprising an anode and a cathode, wherein the cathode is coupled to the phase node terminal; and a comparator comprising a first input terminal coupled to the anode of the diode for receiving a measurement value indicative of a phase voltage at the phase node terminal, a second input terminal coupled to a threshold source for receiving a threshold, and an output terminal configured to output a comparison result indicating whether the measurement value satisfies the threshold. The phase node terminal is configured to be connected to a high-side supply potential by the high-side transistor, and is configured to be connected to a low-side supply potential by the low-side transistor.