Gate Driver Pre-Charging Circuit for LCD Pulse Width Management

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Solution Overview

Problem

As the driving frequency of gate signals increases in liquid crystal display (LCD) apparatuses, the pulse width decreases, leading to signal delays and resulting in driving defects due to insufficient time for pixel charging.

Innovation Solution

A gate driver with a shift register configuration including an (m−1)-th, m-th, and (m+1)-th stage, featuring a first holding part, pre-charging, pull-up, and pull-down components to manage clock signals and output pulses, ensuring adequate charging time for pixels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If driving frequency of gate signal is increased, then productivity is improved, but pulse width decreases causing signal delay and driving defects

Engineering Contradiction:
Improvedriving frequencyVSAvoidpulse width
Core Design Contradiction:
ProductivityVSDuration of action of moving object

Solution Approach 1:

The pre-charging part performs preliminary charging of the output terminal before the main switching operation. By using the output signal from the (m-1)-th stage to activate the pre-charging part, the circuit prepares the voltage level in advance, ensuring that when the gate signal transitions, the charging can begin immediately without waiting for the full pulse width, thus resolving the contradiction between high driving frequency and sufficient charging time

Inventive Principle:
Principle #10Preliminary action

2Productivity

If pulse width of gate signal decreases, then driving frequency increases, but charging time for pixel becomes insufficient

Engineering Contradiction:
Improvedriving frequencyVSAvoidcharging time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The pre-charging part uses the carry signal from the (m-1)-th stage to initiate charging of the output terminal before the main gate signal transition occurs. This preliminary action ensures that the voltage at the output terminal is already prepared, reducing the actual charging time required during the main switching phase and preventing pixel charging deficiencies even at high driving frequencies

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If gate driver is integrated on display panel, then device complexity is reduced, but signal transmission delay increases

Engineering Contradiction:
Improvenumber of chipsVSAvoidsignal transmission delay
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

By integrating the pre-charging part within the gate driver circuit that is directly mounted on the display panel, the invention performs preliminary voltage preparation at the location where the signal will be used. This eliminates the need for separate external chips while ensuring that the signal is ready for immediate transmission, thus reducing both device complexity and signal transmission delay

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8194026B2Gate driver and display apparatus having the same
Publication Date: 2012.06.05 LONESTAR CRYSTAL DISPLAY LLC
  • US8194026B2 patent drawing
  • US8194026B2 patent drawing
  • US8194026B2 patent drawing

AI summary

A gate driver comprises a shift register that has a plurality of stages connected together and outputs a gate signal comprising a first pulse and a second pulse to a gate line. A stage includes a holding part, a pre-charging part, a pull-up part, and a pull-down part. The holding part discharges an output terminal to an off-voltage in response to a first clock signal. The pre-charging part turns off the holding part and outputs the first clock signal as the first pulse to the output terminal in response to an output signal of a previous stage. The pull-up part outputs a second clock signal as the second pulse to the output terminal in response to the output signal of the previous stage. The pull-down part discharges the first output terminal to the off-voltage in response to an output signal of a next stage.