Gate Driver Shift Register With Fast Pull-Down Node Control
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Solution Overview
Problem
Existing gate driving circuits in TFT-LCDs face issues with long operation periods and voltage threshold shifts, making it difficult to control the circuit effectively with control signals.
Innovation Solution
The proposed solution involves a shift register circuit with dual clocks, pre-charging, resetting, and retaining circuits, utilizing transistors with short-circuited source and drain to rapidly control the pulling-down node and reduce voltage threshold shifts, thereby improving circuit control and operation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a basic gate driving circuit is used, then the circuit can operate, but the operation period becomes long and voltage threshold shifts occur
Solution Approach 1:
The patent applies preliminary action by introducing a pre-charging circuit that charges the pulling-up node before the main switching operation. This pre-charging mechanism prepares the circuit in advance, reducing the overall operation period and preventing voltage threshold shifts by ensuring the node is already charged to the appropriate voltage level before switching occurs.
Solution Approach 2:
The patent implements dynamics by using dual clock signals (CK and CKB) that are phase-opposed to dynamically control the switching of transistors. This dynamic control mechanism optimizes the timing of charging and discharging operations, reducing the operation period while maintaining voltage threshold stability through synchronized clocked control.
2Ease of operation
If control signals are applied to the basic circuit, then operation is possible, but control effectiveness is poor due to long operation period and voltage threshold shifts
Solution Approach 1:
The patent applies feedback by using the output signal from one stage to control the next stage in the shift register sequence. This feedback mechanism ensures that control signals are properly synchronized and timed, improving control effectiveness by ensuring that each stage responds to control signals at the optimal moment in the operation cycle.
Solution Approach 2:
The patent implements periodic action through the use of clock signals that periodically control the switching of transistors in each stage. This periodic control ensures that control signals are applied at regular intervals when the circuit is most responsive, improving control effectiveness while maintaining a reduced operation period through efficient timing.
3Device complexity
If transistors are used without short-circuiting source and drain, then circuit structure is simpler, but control over pulling-down node is insufficient
Solution Approach 1:
The patent applies local quality by short-circuiting the source and drain of specific transistors (such as transistor M8 in the retaining circuit) to create localized capacitive effects. This local modification enhances the control over the pulling-down node by creating a capacitance that helps maintain voltage levels and improves control effectiveness without requiring complex circuit restructuring.
Data Source
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AI summary
A shift register, a display apparatus, a gate driving circuit and a driving method, the shift register comprises a plurality of stages of shift register circuits (SR0-SRn), a Nth stage shift register circuit among the plurality of stages of shift register circuits (SR0-SRn) comprises: a pre-charging circuit (1), a pulling-up circuit (2), a resetting circuit (3) and a retaining circuit, the retaining circuit is equipped with an eighth transistor (M8) whose gate is connected with a first control signal terminal (CK), source and drain are connected with each other. Not only a shift registering is realized, but also the operation period of the circuit is decreased, which can address the problem of shift in the voltage thresholds. Further, with the transistor whose source and drain are short-circuited, a control of the control signal on the pulling-down node is realized, so that a potential at the pulling-down node rises rapidly when the first control signal is in the high level and has a reduced descending range when the first control signal is in the low level, which can realize a better control of the circuit.