Gate Driver Q-Node Isolation for Fast, Accurate Pixel Sensing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Display devices, particularly OLEDs, face challenges due to variations in electrical characteristics among pixels, which can lead to inconsistencies in performance over time, affecting contrast ratio and color gamut.
Innovation Solution
A gate driver design incorporating cascade-connected signal transmission units with specific transistors that manage the Q node potential, including pull-up and pull-down transistors, and control signals to reduce capacitive load and enable accurate sensing, ensuring uniform electrical characteristics across pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional gate driver design is used, then device complexity is reduced, but measurement precision and sensing accuracy deteriorate due to inability to accurately sense pixel electrical characteristics
Solution Approach 1:
The gate driver is divided into multiple signal transmission units (first, second, third, and fourth units) that operate in sequence. Each unit contains specific transistors (first pull-up, second pull-up, first pull-down, second pull-down) that can be independently controlled to manage the Q node potential, enabling precise sensing operations without requiring a complete redesign of the entire gate driver structure.
Solution Approach 2:
Before actual pixel sensing, the gate driver performs preliminary actions by controlling the pull-up and pull-down transistors to charge or discharge the Q node capacitance. This preliminary charging/discharging prepares the circuit in a known state, eliminating uncertainty and enabling accurate subsequent measurements of pixel electrical characteristics.
2Productivity
If simple transistor control is used, then device complexity is reduced, but productivity and sensing speed deteriorate due to inability to rapidly charge/discharge capacitance
Solution Approach 1:
Multiple transistors (first pull-up, second pull-up, first pull-down, second pull-down) are combined and controlled in coordination to manage the Q node potential. This merging of multiple control elements enables rapid charging and discharging of the capacitance by distributing the control function across multiple devices that can operate simultaneously or sequentially, significantly increasing sensing speed.
Solution Approach 2:
The gate driver employs dynamic control of transistor states, switching between different configurations of pull-up and pull-down transistors depending on the sensing phase. This dynamic reconfiguration allows the circuit to adapt its impedance and charging/discharging characteristics in real-time, enabling fast capacitance manipulation while maintaining measurement accuracy.
3Manufacturing precision
If uniform transistor control is used, then device complexity is reduced, but manufacturing precision deteriorates due to process deviation and electrical characteristic variations
Solution Approach 1:
Different transistors in the gate driver are assigned specific local functions: pull-up transistors are optimized for charging the Q node, while pull-down transistors are optimized for discharging it. This local specialization allows each transistor to be tuned for its specific role, compensating for process variations and ensuring that electrical characteristics remain uniform across different pixels despite manufacturing deviations.
Solution Approach 2:
The gate driver incorporates feedback mechanisms where the state of the Q node is continuously monitored through the coordinated action of pull-up and pull-down transistors. This feedback allows the circuit to detect and compensate for variations in transistor characteristics, maintaining uniform electrical performance across all pixels by adjusting the sensing operation based on actual measured conditions.
Data Source
AI summary
The present specification discloses a gate driver including first and second pull-up transistors, first and second pull-down transistors, a first output terminal configured to output a carry signal, an Ath transistor disposed between the first and second pull-up transistors and configured to electrically separate a Q node in response to a control signal, a Bth transistor disposed between the Ath and second pull-up transistors and configured to supply a low potential voltage to the second pull-up transistor in response to a control bar signal, and a Cth transistor connected to the second output terminal to supply the low potential voltage in response to the control bar signal. According to the present specification, by reducing a capacitive load compared to the related art at the same time upon sensing for electrical characteristic compensation of a pixel circuit, it is possible to quickly charge a capacitance and enable accurate sensing.