Gate Driver QB Node Control for Higher-Resolution Narrow Bezels

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Solution Overview

Problem

As display resolution increases, the number of gate stages in display apparatuses increases, leading to an inevitable expansion of the bezel area, limiting the ability to reduce the bezel size.

Innovation Solution

A gate driver design that includes a pull-up transistor, pull-down transistor, and QB node controller, utilizing an AC-type control power source with on and off levels during different frame periods, to simplify gate stage configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the number of gate stages is increased to support higher display resolution, then the display resolution is improved, but the bezel area increases

Engineering Contradiction:
Improvedisplay resolutionVSAvoidbezel area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent combines multiple transistors into integrated transistor groups within each gate stage. Specifically, it merges the pull-up transistor, pull-down transistor, and QB node control transistors into a compact configuration where they share common nodes and control structures, reducing the overall area occupied by each gate stage and thus the total bezel area.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The control power source is designed to serve multiple functions: it provides control voltage to the QB node controller, which in turn controls both the pull-up and pull-down transistors. This multi-functional design reduces the need for separate control circuits, simplifying the gate stage structure and reducing bezel area.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If the number of gate stages is increased to support higher display resolution, then the display resolution is improved, but the device complexity increases

Engineering Contradiction:
Improvedisplay resolutionVSAvoidgate stage configuration complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent utilizes parameter changes in the control power source voltage to control the operation state of the QB node controller, which in turn controls the pull-up and pull-down transistors. By changing the control voltage parameter, the system can switch between different operational states (on/off levels) without requiring complex control logic, thereby simplifying the gate stage configuration.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If more transistors are used in each gate stage to improve functionality, then the control precision is improved, but the device complexity increases

Engineering Contradiction:
Improvecontrol precisionVSAvoidtransistor configuration complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges multiple transistors into compact groups within each gate stage, where transistors share common control nodes and power connections. This merging reduces the spatial complexity and interconnection complexity while maintaining the functional precision required for controlling the gate lines.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The QB node controller acts as an intermediary between the control power source and the pull-up/pull-down transistors. It receives control voltage from the power source and translates it into appropriate control signals for the transistors, simplifying the overall control architecture while maintaining precise control capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250259602A1Gate driver and display apparatus including the same
Publication Date: 2025.08.14 LG DISPLAY CO LTD
  • US20250259602A1 patent drawing
  • US20250259602A1 patent drawing
  • US20250259602A1 patent drawing

AI summary

A gate driver and a display apparatus including the same are discussed. The gate driver can include a plurality of stages. An nth stage among the plurality of stages includes a pull-up transistor configured to control a flow of a current between an output node and an input terminal for an nth clock based on a voltage of a Q node, a pull-down transistor configured to control a flow of a current between the output node and an input terminal of a first low power source based on a voltage of a QB node, and a QB node controller configured to control the voltage of the QB node based on a voltage of a control power source and the voltage of the Q node, where n is an integer.