Dual Shift Register Gate Driver for Random Pixel Sensing

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Solution Overview

Problem

Display devices experience a horizontal line phenomenon during pixel sensing operations, causing visible rows of pixels from the outside due to sequential gate signal application.

Innovation Solution

A gate driver system with dual shift registers and switches that selectively generates gate signals and sensing signals, allowing random selection of pixel rows for sensing during vertical blank periods, using different start pulses and clock signals to prevent row visibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If sequential gate signal application is used for sensing operations, then pixel sensing can be performed, but horizontal lines become visible during sensing

Engineering Contradiction:
Improvesensing operationVSAvoidhorizontal line visibility
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies dynamics by making the gate signal application pattern variable rather than fixed. The controller randomly determines the application timing of gate signals during vertical blank periods, changing the temporal distribution pattern from sequential to random. This dynamic adjustment prevents the formation of visible horizontal lines while maintaining sensing functionality.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements preliminary action by performing random timing determination before the actual gate signal application. The controller pre-determines when gate signals will be applied during vertical blank periods, ensuring that sensing operations are prepared and scheduled in advance with random timing to avoid visible patterns.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If gate signals are applied sequentially to all pixel rows, then complete sensing coverage is achieved, but visual artifacts appear

Engineering Contradiction:
Improvesensing coverageVSAvoidvisual artifacts
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent uses dynamics to transform the static sequential gate signal application into a dynamic random application pattern. By randomly determining gate signal timing for each frame during vertical blank periods, the system maintains comprehensive sensing coverage while eliminating the predictable patterns that cause visual artifacts.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies parameter changes by modifying the temporal parameters of gate signal application. Instead of fixed sequential timing, the system varies the timing parameters randomly for each frame, changing the moment of gate signal application within vertical blank periods to prevent artifact formation while preserving measurement coverage.

Inventive Principle:
Principle #35Parameter changes

3Object-affected harmful factors

If random gate signal timing is used, then horizontal lines are prevented, but control complexity increases

Engineering Contradiction:
Improvehorizontal line preventionVSAvoidcontrol mechanism
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent applies universality by making the controller perform multiple functions: it manages normal display operations, determines random gate signal timing for sensing, and handles vertical blank period coordination. By consolidating these functions in the existing controller rather than adding dedicated hardware, the system achieves horizontal line prevention without proportionally increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12555543B2Gate driver and display device including the same
Publication Date: 2026.02.17 SAMSUNG DISPLAY CO LTD
  • US12555543B2 patent drawing
  • US12555543B2 patent drawing
  • US12555543B2 patent drawing

AI summary

A gate driver includes a first shift register connected to gate lines, and configured to supply a gate signal to the gate lines in response to a first start pulse, and a second shift register connected to the gate lines and sensing control lines, and configured to supply the gate signal and a sensing signal to the gate lines and the sensing control lines in response to a second start pulse, in which the second shift register is configured to supply the second start pulse at different times in sequential frames.