Multiphase Gate Driver Shift Register Reset for Flicker Prevention
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Solution Overview
Problem
Existing gate drivers in display devices often produce undesired output signals, leading to malfunctions such as screen flickering due to the degradation of transistors, which affects the reliability of the display.
Innovation Solution
A gate driver design that utilizes a plurality of shift registers connected in cascade and driven by multiphase clocks, where the next shift register is reset using an output signal from the previous shift register, preventing simultaneous output signals and ensuring desired timing of output signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shift registers are connected in cascade with conventional reset timing, then the gate driver can operate continuously, but undesired output signals occur due to transistor degradation
Solution Approach 1:
The patent applies preliminary action by resetting the next shift register in advance before it generates undesired output signals. The reset timing is shifted so that each shift register is reset by its previous counterpart before it can produce harmful outputs, preventing screen flickering and malfunction while maintaining continuous operation
Solution Approach 2:
The patent converts the harmful effect of transistor degradation into a beneficial timing mechanism. By utilizing the degraded transistor's output signal to reset the next shift register, the harmful signal is transformed into a useful reset control signal that prevents future undesired outputs, turning reliability degradation into a preventive mechanism
2Speed
If multiple shift registers operate simultaneously with the same clock phase, then the gate driver achieves high speed operation, but simultaneous output signals cause malfunctions
Solution Approach 1:
The patent segments the clocking operation by dividing shift registers into different groups that operate with different clock phases. This segmentation allows simultaneous operation at high speed while preventing simultaneous output signals that would cause malfunctions, as each group operates in a staggered manner
Solution Approach 2:
The patent implements periodic action through multiphase clocking where shift registers are driven by clocks with different phases. This creates a periodic, staggered operation pattern that maintains high speed performance while ensuring that output signals from different shift registers do not occur simultaneously, preventing signal conflicts
Data Source
AI summary
A gate driver includes a plurality of shift registers connected in cascade to each other and driven by a plurality of multiphase clocks, respectively, wherein the next shift register to which one of the plurality of multiphase clocks is applied is reset using an output signal outputted from the previous shift register in response to the one of the plurality of multiphase clocks.