Gate Driver Logic Timing for LCD Row Signal Synchronization
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Solution Overview
Problem
In TFT-LCD driving circuits, the delay of the gate driving signal causes data mix at pixel electrodes due to the falling edge of the Gate signal not being synchronized with the next row's rising edge, affecting image quality.
Innovation Solution
A gate driver with a processing circuit that includes a NOT gate, D flip-flop, AND gates, logic combination circuits, and selection circuits processes the CPV, OE, and STV signals to introduce a preset time interval between the edges of the CKV and CKVB signals, ensuring proper timing and preventing data mix.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate driving circuit outputs gate driving signals to turn on gate lines sequentially, then the display can be driven, but the falling edge of the Gate signal delays causing data mix at pixel electrodes
Solution Approach 1:
The patent introduces a preset time interval between the falling edge of the CKV signal and the rising edge of the CKVB signal. This time interval ensures that the data input for the next row is completely finished before the gate driving signal for the current row falls, preventing data mix and ensuring precise data input synchronization.
2Reliability
If the STV signal level is converted to match the gate driving circuit requirements, then proper gate driving is achieved, but the complexity of the driving circuit increases
Solution Approach 1:
The patent introduces a processing circuit as an intermediary component that receives the STV signal from the timing controller and generates the appropriately level-converted CKV and CKVB signals. This processing circuit acts as a mediator between the timing controller and the gate driving circuit, ensuring reliable signal level matching without requiring direct complex integration.
Data Source
AI summary
There is disclosed a gate driver, a driving circuit, and a liquid crystal display (LCD), wherein the gate driver comprises input terminals for inputting a CPV signal, an OE signal, and an STV signal, and output terminals for outputting a CKV signal and a CKVB signal, and a processing circuit is connected between the input terminals and the output terminals for processing the CPV signal, the OE signal, and the STV signal such that a preset time interval is present between the falling edge of the CKV signal and the rising edge of the CKVB signal during one period of the CKV signal, or a preset time interval is present between the rising edge of the CKV signal and the falling edge of the CKVB signal during one period of the CKVB signal.