Integrated Gate Driver Circuit for Scan and Sensing Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing gate drivers in display devices require larger sizes due to separate shift registers for scan and sensing signals, leading to increased dead space in the display panel.
Innovation Solution
A gate driver design that integrates a single stage to output both scan and sensing signals using a shared QB node and QB node controlling circuit, allowing for a compact structure and reduced dead space, with sequential output of signals in active and self-scan periods, and simultaneous operation in overlapping periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate shift registers are used for scan and sensing signals, then signal output reliability is improved, but gate driver size increases
Solution Approach 1:
The patent combines two separate shift registers (scan shift register and sensing shift register) into a single integrated shift register structure. This single shift register sequentially outputs both scan signals and sensing signals, reducing the gate driver area while maintaining signal output reliability through proper signal separation circuits that prevent voltage interference between the two signal types.
Solution Approach 2:
The single shift register is designed to perform multiple functions by sequentially generating both scan signals and sensing signals. The circuit includes control mechanisms that enable the same shift register structure to serve dual purposes: driving scan operations and performing sensing operations, thereby reducing overall circuit complexity and area.
2Reliability
If separate shift registers are used for scan and sensing signals, then signal separation is improved, but device complexity increases
Solution Approach 1:
The patent merges the functionality of separate shift registers into a single integrated structure that sequentially produces both scan and sensing signals. This reduces device complexity by eliminating redundant circuit elements while incorporating signal separation mechanisms within the unified structure to maintain proper signal differentiation.
Solution Approach 2:
The circuit employs dynamic control mechanisms including clock signal management and node voltage control that adaptively switch between generating scan signals and sensing signals. The dynamic control of QB nodes and carry signals enables the single shift register to flexibly perform different functions at different time periods, reducing static circuit complexity.
Data Source
AI summary
A stage of a gate driver includes a sensing input circuit a sensing input signal, a scan input circuit, a Q node separating circuit between a sensing Q node and a scan Q node, a QB node controlling circuit, a sensing carry circuit configured to output a sensing carry signal based on a voltage of the sensing Q node and a voltage of a shared QB node, a sensing output circuit configured to output a sensing signal based on the voltage of the sensing Q node and the voltage of the shared QB node, a scan carry circuit configured to output a scan carry signal based on a voltage of the scan Q node and the voltage of the shared QB node, and a scan output circuit configured to output a scan signal based on the voltage of the scan Q node and the voltage of the shared QB node.