Gate Driver Shift Register Timing for Reliable Display Scanning
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Solution Overview
Problem
Existing display devices face challenges in improving reliability, particularly in the synchronization and timing of scan signals within the gate driver, which affects the overall performance and longevity of the display.
Innovation Solution
The display device incorporates a shift register with staggered flip-flops and clock generators that generate internal inversion clocks, ensuring precise timing of output signals, with each carry signal being delayed by half the horizontal scan period, and includes a level shifter to adjust voltage levels for accurate scan signal output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional shift register is used in the gate driver, then the device complexity is reduced, but the synchronization and timing precision of scan signals deteriorates
Solution Approach 1:
The shift register is divided into multiple stages, with each stage containing separate first and second flip-flops. The first flip-flop generates output signals while the second flip-flop generates carry signals with half-period delay. This segmentation allows independent control of timing parameters for different signal types, achieving precise synchronization without requiring a complete redesign of the entire shift register architecture.
Solution Approach 2:
The carry signals are generated in advance with a predetermined half-period delay through the second flip-flop stage. This preliminary action ensures that the timing relationships between scan signals are established before they are applied to the display panel, enabling precise synchronization control while maintaining a relatively simple overall circuit structure.
2Reliability
If scan signals are generated without precise timing control, then the device complexity is reduced, but the reliability of the display device deteriorates
Solution Approach 1:
Different stages of the shift register are assigned different local functions: the first flip-flop in each stage is optimized for generating output scan signals, while the second flip-flop is optimized for generating carry signals with specific timing characteristics. This local differentiation ensures that each part of the circuit contributes to the overall reliability through its specialized function, achieving good signal synchronization without requiring complex global control mechanisms.
3Productivity
If the horizontal scan period is reduced to improve refresh rate, then the productivity is improved, but the timing precision of individual scan signals deteriorates
Solution Approach 1:
The shift register operates with periodic clock signals to generate scan signals at different time points within each horizontal scan period. By using periodic action with multiple phases (through the first and second flip-flops), the system can maintain precise timing relationships even when the overall period is reduced, allowing high refresh rates without sacrificing individual signal timing precision.
Data Source
AI summary
Disclosed is a display device including a display panel including a pixel, a gate driver including a shift register that outputs output signals, and a data driver that supplies a data voltage to the pixel. The shift register includes a first stage that receives a start signal and outputs a first output signal among the output signals and a first carry signal, and a second stage that receives the first carry signal and outputs a second output signal among the output signals and a second carry signal. The first carry signal is a signal delayed from the first output signal, and the second carry signal is a signal delayed from the second output signal.