Gate Driver Segmentation for Display Power Reduction
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Solution Overview
Problem
Display apparatuses face challenges in reducing power consumption and preventing flicker due to current leakage when driving gate lines, especially in static image modes, where existing methods often result in increased dead space and inefficiencies.
Innovation Solution
A gate driver that divides and drives gate lines into two groups using only two gate clock lines, adjusting the driving frequency based on image data to optimize power usage and minimize flicker, by outputting gate signals to odd or even numbered lines in alternating frames or subframes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the gate driver divides gate lines into two groups for low frequency driving, then power consumption is reduced, but the number of clock lines must be doubled which increases dead space
Solution Approach 1:
The gate lines are segmented into two groups (first group and second group) that are driven alternately at different times. The first stage drives the first group of gate lines while the second stage drives the second group of gate lines, enabling low frequency driving by reducing the number of active clock lines from four to two.
Solution Approach 2:
The gate driver dynamically adjusts which clock lines are active based on the driving mode. In low frequency driving mode, only two clock lines are used alternately, while in high frequency driving mode, all four clock lines are used. This dynamic adaptation allows the system to optimize between power consumption and driving performance.
2Productivity
If the gate driver uses four clock lines for driving gate lines, then high frequency driving is achieved, but dead space increases and power consumption rises
Solution Approach 1:
The gate driver dynamically switches between different clock line configurations based on driving requirements. When high driving frequency is needed, all four clock lines are activated. When low driving frequency is sufficient, the system uses only two clock lines alternately, thereby reducing power consumption while maintaining the ability to achieve high frequency when necessary.
Solution Approach 2:
The system changes the operating parameters by selecting different clock line combinations based on the driving mode. The control unit adjusts which clock lines are active, changing the temporal and spatial utilization of clock signals to optimize the balance between driving frequency and power consumption.
3Reliability
If the gate driver drives all gate lines at high frequency, then image quality is maintained, but power consumption increases significantly
Solution Approach 1:
The gate lines are divided into multiple groups that can be driven independently at different frequencies. The first group of gate lines is driven at a first frequency while the second group is driven at a second frequency, allowing the system to maintain image quality through periodic scanning while significantly reducing overall power consumption compared to driving all lines at high frequency continuously.
Solution Approach 2:
The gate driver uses periodic scanning of gate line groups. Instead of continuously driving all gate lines at high frequency, the system periodically scans through different groups of gate lines at lower frequencies, maintaining image quality through the periodic refresh while reducing power consumption during periods when not all lines need to be updated.
Data Source
AI summary
A gate driver includes a first stage, a second stage, a third stage and a fourth stage. The first stage includes a first clock terminal receiving a first clock signal, a second clock terminal receiving a second clock signal, a carry terminal receiving a vertical start signal and an output terminal outputting a first gate output signal. The second stage includes a first clock terminal receiving the second clock signal, a second clock terminal receiving the first clock signal, a carry terminal receiving the vertical start signal and an output terminal outputting a second gate output signal. The third stage includes a first clock terminal receiving the second clock signal, a second clock terminal receiving the first clock signal, a carry terminal receiving the first gate output signal and an output terminal outputting a third gate output signal.