Gate Driver Segmentation for Display Signal Stability
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Solution Overview
Problem
The increasing size and resolution of display panels lead to higher loads and parasitic capacitance in gate lines, causing instability and unreliability in gate drivers due to broken waveforms of output signals, which deteriorate display quality.
Innovation Solution
A gate driver is designed with a carry signal generating circuit and a shift register circuit, including specific transistor configurations and capacitors, to stabilize the output of gate signals by generating and processing carry signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the display panel size and resolution are increased, then the display quality is improved, but the gate line load and parasitic capacitance increase causing waveform breakdown
Solution Approach 1:
The gate driver is divided into multiple independent stages (first stage, second stage, third stage, etc.), each with its own carry signal generating circuit and shift register circuit. This segmentation allows each stage to independently handle a portion of the gate lines, reducing the load on individual stages and preventing waveform breakdown while maintaining the ability to drive large high-resolution displays.
2Quantity of substance
If the gate driver drives more pixels with higher load, then the display resolution is improved, but the output signal waveform becomes broken
Solution Approach 1:
Each stage generates its carry signals (first and second carry signals) in advance through the carry signal generating circuit before they are needed by the shift register circuit. This preliminary generation of carry signals ensures that the shift register has the necessary control signals ready to maintain stable waveform output even when driving a large number of pixels with high load conditions.
3Speed
If the clock signal frequency is increased for high-speed driving, then the driving speed is improved, but the gate driver reliability is reduced
Solution Approach 1:
The multi-stage architecture segments the high-frequency clock signal processing across multiple independent stages. Each stage operates at the high clock frequency but handles a limited portion of the total pixel load, which distributes the timing stress and prevents cumulative waveform degradation that would occur in a single-stage design, thereby maintaining reliability at high speeds.
Data Source
AI summary
A gate driver includes a carry signal generating circuit and a shift register circuit. The carry signal generating circuit receives a vertical start signal and outputs first and second carry signals. The shift register circuit receives the first and second carry signals and outputs a first stage first carry signal, a first stage second carry signal and a first stage gate output signal. The carry signal generating circuit includes a first carry generator generating the first carry signal and a second carry generator generating the second carry signal. The shift register circuit includes a first stage first carry generator generating the first stage first carry signal, a first stage second carry generator generating the first stage second carry signal and a first stage output buffer outputting the first stage gate output signal.