Gate Driver Hold-Signal Circuit for Low-Power Self-Scan Displays
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Solution Overview
Problem
Display devices experience power consumption issues during self-scan mode due to frequency mismatches between rendering and driving frequencies, leading to inefficiencies.
Innovation Solution
A gate driver design with transistors and control circuits that manage voltage levels and clock signals to optimize power consumption by disabling toggling during self-scan mode, using a hold signal to maintain stable off-voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the display device operates in self-scan mode to synchronize rendering frequency with driving frequency, then the tearing phenomenon is prevented, but power consumption increases due to continuous clock signal toggling
Solution Approach 1:
The patent applies periodic action by enabling clock signal toggling only during the address scan period and disabling it during the self-scan period. This periodic enable/disable mechanism reduces power consumption while maintaining the tearing prevention benefit during self-scan mode operation.
Solution Approach 2:
The patent changes the operational parameter of clock signal toggling based on the scanning mode. During self-scan mode, the clock signal toggling is disabled (parameter change from active to inactive), thereby reducing power consumption while maintaining synchronization between rendering and driving frequencies.
2Use of energy by moving object
If clock signal toggling is disabled during self-scan mode to reduce power consumption, then energy efficiency improves, but voltage stability may be compromised
Solution Approach 1:
The patent introduces a hold signal as an intermediary mechanism that maintains voltage stability at the output node even when clock signal toggling is disabled. The hold signal acts as a mediator between the disabled clock signal and the required voltage stability, ensuring that voltage levels remain stable during self-scan mode.
Solution Approach 2:
The patent applies preliminary action by using the hold signal to prepare and maintain the output node voltage before and during the self-scan period. This preliminary maintenance of voltage levels ensures stability is established in advance, preventing voltage fluctuations when clock toggling is disabled.
Data Source
AI summary
A gate driver according to an embodiment includes a plurality of stages connected to a plurality of gate signal lines. Each of the plurality of stages may include a first transistor connected between a first terminal and an output node and transmitting a voltage of the first terminal to the output node in response to a voltage of a first control node, a second transistor connected between a second terminal and the output node and transmitting a voltage of the second terminal to the output node in response to a voltage of the second control node, and a third transistor diode-connected between the second control node and a third terminal to which a hold signal is input. The hold signal may maintain a first voltage during a first period and maintain a second voltage, different from the first voltage, during a second period.