Gate Driver Circuit for Display Devices with Sensing Mode Compensation
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Solution Overview
Problem
Existing display devices, particularly organic light-emitting display devices, face challenges in efficiently compensating for the deterioration of driving thin film transistors over time, which affects the accuracy and longevity of image reproduction, especially when operating in sensing modes where current sensing methods can interfere with light emission.
Innovation Solution
A gate driver system is introduced that includes a first circuit unit for charging or discharging control nodes and a second circuit unit with buffer transistors to output gate signals based on clock signals and low potential voltages, allowing for sensing mode operations without light emission by altering the voltage levels used during pixel circuit driving.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If current sensing-based compensation method is used to compensate for driving TFT deterioration, then compensation accuracy is improved, but the OLED may be recognized as emitting light during sensing operation
Solution Approach 1:
The patent implements dynamic switching between display mode and sensing mode by controlling the voltage levels of clock signals and low potential voltages. During sensing mode, the system dynamically adjusts the voltage levels to prevent light emission while maintaining sensing functionality, resolving the contradiction between accurate measurement and unwanted light emission.
Solution Approach 2:
The patent changes the voltage parameters (clock signal voltage and low potential voltage levels) based on the operating mode. By adjusting these voltage parameters, the system can operate in sensing mode without causing the OLED to emit light, while still achieving accurate current sensing for compensation purposes.
2Duration of action of stationary object
If sensing mode operation is implemented to compensate for element deterioration, then device longevity is improved, but visibility issues occur during sensing due to light emission
Solution Approach 1:
The system dynamically switches between display and sensing modes with distinct voltage level configurations. During sensing mode, the adjusted voltage levels prevent light emission, ensuring the display remains visually stable while enabling continuous deterioration compensation that extends device longevity.
Solution Approach 2:
By changing the voltage parameters (using high level voltage for low potential voltage during sensing mode), the system enables sensing operations without unwanted light emission, thus maintaining device longevity while avoiding visibility issues during sensing.
3Device complexity
If standard gate signal output is used during sensing mode, then circuit simplicity is maintained, but sensing accuracy deteriorates due to light emission interference
Solution Approach 1:
The patent modifies the voltage parameters of the gate signal during sensing mode (using high level voltage for low potential voltage) to prevent light emission. This parameter change improves sensing accuracy while maintaining the existing circuit structure, thus achieving better measurement precision without significantly increasing device complexity.
Data Source
AI summary
A gate driver according to an embodiment and a display device using the same are discussed. The gate driver can output a gate signal to a pixel circuit having a driving element connected between a first power line and a first node, a light-emitting element connected between the first node and a second power line, and a switching element connected between the first node and a third power line and driven by the gate signal. The gate driver includes a first circuit unit to receive a carry signal from a previous signal transmission unit to charge or discharge a first control node and a second control node, and a second circuit unit having a first buffer transistor and a second buffer transistor configured to output the gate signal based on a first clock signal and a first low potential voltage according to potentials of the first and second control nodes.