Gate Driver Circuit With Separated Control Nodes for Compact Outputs
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Solution Overview
Problem
The integration of a large number of transistors and signal wires in gate drivers within display devices increases dead space and power consumption.
Innovation Solution
A gate driver design that includes a control circuit, node separation transistor, and gate output circuits, where the control circuit controls a first control node in response to a clock signal, and the node separation transistor separates the first and second control nodes, allowing the gate output circuits to share these components, thereby reducing the number of transistors and signal wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the gate driver integrates more transistors and signal wires to provide multiple gate signals, then the functionality and versatility improve, but the dead space and power consumption increase
Solution Approach 1:
Multiple gate output circuits share common control nodes (first control node and second control node) and control circuits, merging previously separate components into shared resources. This reduces the total number of transistors and signal wires while maintaining the capability to output multiple gate signals with different timings.
Solution Approach 2:
The first control node and second control node serve multiple functions simultaneously - they control multiple gate output circuits and enable multiple gate signals to be generated from a single stage. The control circuit performs multiple control functions using shared components, making the circuit universally applicable to multiple output requirements.
2Adaptability or versatility
If the gate driver integrates more transistors and signal wires to provide multiple gate signals, then the functionality and versatility improve, but the power consumption increases
Solution Approach 1:
Multiple gate output circuits share common control nodes (first control node and second control node) and control circuits, merging previously separate components into shared resources. This reduces the total number of transistors and signal wires while maintaining the capability to output multiple gate signals with different timings.
Solution Approach 2:
The first control node and second control node serve multiple functions simultaneously - they control multiple gate output circuits and enable multiple gate signals to be generated from a single stage. The control circuit performs multiple control functions using shared components, making the circuit universally applicable to multiple output requirements.
3Reliability
If the control nodes are separated to improve reliability, then the reliability improves, but the device complexity increases
Solution Approach 1:
The control circuit is segmented into distinct functional blocks: an input circuit receiving clock signals, a control circuit generating control signals based on input signals and clock signals, and separate first and second control nodes that are electrically separated. This segmentation isolates control functions and improves reliability by preventing error propagation between nodes.
Solution Approach 2:
The control circuit acts as an intermediary between the input circuit and the gate output circuits. It receives clock signals and input signals, processes them to generate appropriate control signals, and distributes these control signals to the first and second control nodes, which then independently control the gate output circuits. This intermediary structure manages complexity while maintaining reliability.
Data Source
AI summary
A gate driver includes a plurality of stages. At least one of the stages includes a control circuit configured to control a first control node in response to a first carry clock signal, a node separation transistor connected between the first control node and a second control node, a carry output circuit configured to output a carry signal in response to a voltage of the second control node, and a plurality of gate output circuits configured to output a plurality of gate signals having different timings in response to the voltage of the second control node.