Gate Driver Dead-Time Control With a Single Shared Timer
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Solution Overview
Problem
Power converters face the issue of shoot-through, where a direct short occurs between the input voltage and ground due to simultaneous conductivity of high-side and low-side electrically-controlled switches, leading to potential damage and inefficiency, despite efforts to prevent it through timing control.
Innovation Solution
A gate driver is implemented with a timer-based system that inserts delay times between the de-assertion of the drive-high terminal and assertion of the drive-low terminal, and vice versa, using a single timer to reduce variance and prevent simultaneous conductivity, thereby mitigating shoot-through.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay time is inserted between switching operations of high-side and low-side FETs, then the risk of shoot-through is reduced, but the transition timing precision deteriorates due to variance in delay times
Solution Approach 1:
The patent merges the functionality of multiple separate delay circuits into a single shared timer circuit. This timer generates delay periods for both high-side and low-side FET switching operations, ensuring that both delays are derived from the same time reference. By combining these functions, the patent eliminates variance between separate delay circuits and achieves precise, consistent transition timing while maintaining shoot-through prevention.
Solution Approach 2:
The timer circuit is designed to serve multiple functions: it generates delay periods for both high-side and low-side FET switching, and also provides timing references for the state machine controller. This multi-functional design reduces the overall number of components and ensures that all timing-critical operations use a unified time base, thereby improving transition timing precision while maintaining reliability.
2Ease of operation
If separate delay circuits are used for high-side and low-side FETs, then switching control is simplified, but delay time variance increases causing imprecise transitions
Solution Approach 1:
The patent combines multiple delay generation functions into a single timer circuit that serves both high-side and low-side FET switching operations. This eliminates the need for separate delay circuits while maintaining the simplicity of switching control. The unified timer ensures that both delays are consistent and precise, resolving the trade-off between control simplicity and delay consistency.
3Manufacturing precision
If multiple timers are used to achieve precise delay times, then transition precision is improved, but device complexity increases
Solution Approach 1:
The patent designs a single timer circuit that performs multiple timing functions: generating delay periods for high-side FET switching, generating delay periods for low-side FET switching, and providing timing references for the state machine. This multi-functional approach achieves precise delay times without requiring multiple separate timers, thereby reducing device complexity while maintaining high transition precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the variance in delay times, minimizing the risk of shoot-through and ensuring reliable operation of power converters by ensuring controlled transitions between conductive states of high-side and low-side FETs.
Implementation Method 1
a capacitor defining a first lead coupled to the current output, and a second lead coupled to a reference voltage
Data Source
AI summary
Operating a gate driver. At least one example is a method of operating the gate driver, the method comprising: de-asserting a drive-low terminal of the gate driver; starting a single timer within the gate driver; and after expiration of the single timer asserting a drive-high terminal of the gate driver responsive to assertion of an in-high terminal of the gate driver; and then de-asserting the drive-high terminal; starting the single timer; and after a second expiration of the single timer asserting the drive-low terminal responsive to assertion of an in-low terminal of the gate driver.