Gate Driver Shift Register for Arbitrary Scan Line Count
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Solution Overview
Problem
Existing gate drivers for large-size thin film transistor liquid crystal display devices (TFT-LCD) face issues with color shift at large view angles and inefficiencies in driving scan lines, particularly with configurations that result in wasted output channels and complex voltage level settings due to non-divisible numbers of output channels.
Innovation Solution
A gate driver design comprising an input buffer, shift register with n+2 triggers, a voltage level shifter, and an output buffer, allowing for arbitrary adjustment of output channels by serially connecting triggers and applying clock signals to enable efficient scanning of any number of scan lines, ensuring universality across configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional gate drivers with fixed output channel numbers (divisible factors of 1080) are used, then the device complexity is reduced and ease of manufacture is improved, but the adaptability to different scan line configurations deteriorates and wasted output channels occur
Solution Approach 1:
The gate driver employs a dynamic configuration where the shift register can be adjusted to provide different numbers of output channels based on the specific scan line requirements. The circuit allows flexible programming of the output channel count, enabling adaptation to various display resolutions and scan line configurations without being fixed to predetermined values.
Solution Approach 2:
The gate driver design achieves universality by implementing a single circuit architecture that can function across multiple configurations. By using a programmable shift register with adjustable trigger count, the same gate driver can serve different display panel types and resolutions, eliminating the need for multiple specialized driver designs.
2Adaptability or versatility
If additional gate drivers are added to support the 1081st scan line, then the adaptability to LCS configuration is improved, but the device complexity increases and wasted output channels occur
Solution Approach 1:
The invention merges the functionality of multiple gate drivers into a single integrated circuit. By combining the shift register, output buffers, and control logic into one unified gate driver, the design eliminates the need for separate additional drivers while still providing the capability to drive all 1081 scan lines required for LCS configurations.
Solution Approach 2:
The gate driver is designed with the capacity to generate more output channels than the minimum required, allowing it to cover the 1081st scan line and potentially accommodate future higher-resolution displays. This excessive capability ensures the driver can handle current and future requirements without modification.
3Adaptability or versatility
If the numbers of output channels in cascaded gate drivers are made different to support 1081 scan lines, then the adaptability to LCS is improved, but the ease of operation deteriorates due to complex voltage level settings
Solution Approach 1:
The gate driver utilizes parameter changes in the voltage level shifter to automatically adapt to different output channel configurations. By programmatically adjusting the voltage level shift parameters based on the configured number of output channels, the system maintains ease of operation while supporting flexible scan line distributions required for LCS configurations.
Data Source
AI summary
The present invention provides a gate driver and liquid crystal display device. The gate driver, for driving scan lines of liquid crystal display device, includes: an input buffer, for receiving clock signal, first frame start pulse signal and second frame start pulse signal; shift register, including n+2 triggers, connected serially from the first trigger to the n+1st trigger, a clock signal input terminal of the n+2nd trigger being connected to the clock signal transmission line, wherein n being a natural number, when the first frame start pulse signal starting, the shift register shifting vertical synchronization signal and outputting n+1 outputs of shift registers based on the clock signal; a voltage level shifter, for shifting the output of the shift register to predefined voltage level and outputting shifted result serially; and an output buffer, for applying output of voltage level shifter to scan lines.