Gate Driver Shift Register Stabilizing Oxide TFT Threshold Voltage

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Solution Overview

Problem

Display devices using oxide TFTs face instability due to threshold voltage shifting, leading to horizontal stripe phenomena that affect image quality.

Innovation Solution

A gate driver is designed with a shift register and mask configuration that synchronizes carry signals with clock signals and generates gate signals based on mask signals, using capacitor coupling to stabilize operation even under stress conditions, allowing selective generation of gate signals for specific pixel rows.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If oxide TFTs are used in the gate driver, then the display device can be manufactured with certain advantages, but the gate driver operates unstably due to threshold voltage shifting

Engineering Contradiction:
Improvemanufacturing advantageVSAvoidoperation stability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent changes the voltage level parameter by providing a boosted voltage (second voltage level) to the gate driver circuit. This voltage boosting compensates for the threshold voltage shifting in oxide TFTs, allowing the gate driver to operate stably despite the inherent instability of oxide TFTs under stress conditions

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If a gate driver is designed to selectively generate gate signals for certain pixel rows, then horizontal stripe phenomena can be reduced, but the device complexity increases

Engineering Contradiction:
Improvehorizontal stripe phenomenonVSAvoidgate driver structure
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The gate driver is divided into multiple gate sub-drivers, each responsible for driving specific pixel rows. Each gate sub-driver includes independent shift registers and mask circuits that can selectively generate gate signals for their assigned pixel rows. This segmentation allows selective driving of pixel rows to reduce horizontal stripe phenomena while managing complexity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A mask circuit acts as an intermediary between the shift register and the output stage. The mask circuit receives carry signals from the shift register and mask signals controlling which pixel rows should be activated. This intermediary component enables selective generation of gate signals without requiring complete redesign of the entire gate driver structure

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If sequential operation of pixels is used, then the gate driver can provide gate signals in order, but horizontal stripe phenomena occur due to sequential detection

Engineering Contradiction:
Improvesequential gate signal provisionVSAvoidhorizontal stripe phenomenon
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The gate driver uses periodic clock signals to control the shift registers in each gate sub-driver. By synchronizing the operation of multiple gate sub-drivers with periodic clock cycles and using mask signals to selectively activate certain pixel rows within each period, the system maintains ease of sequential operation while reducing horizontal stripe phenomena through selective row driving

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS10198998B2Gate driver shift register and mask circuit and display device using the same
Publication Date: 2019.02.05 SAMSUNG DISPLAY CO LTD
  • US10198998B2 patent drawing
  • US10198998B2 patent drawing
  • US10198998B2 patent drawing

AI summary

There is provided a gate driver including a plurality of gate sub-drivers electrically connected to a plurality of gate lines, wherein an (n)th gate sub-driver, of the gate sub-drivers includes a shift register configured to receive an (n−1)th carry signal from an (n−1)th gate sub-driver of the gate sub-drivers adjacent to the (n)th gate sub-driver, to synchronize the (n−1)th carry signal with a first clock signal, and to output an (n)th carry signal based on the synchronized (n−1)th carry signal, and a mask configured to output a gate signal based on the synchronized (n−1)th carry signal and a mask signal, wherein n is an integer greater than or equal to 2.