Gate Driver Signal Delay Circuit for TFT-LCD Power-On Stability
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Solution Overview
Problem
In TFT-LCD displays, abnormal pictures occur during power-on due to incomplete establishment of internal potential in the source driver chip, as the gate driver chip starts working normally before the source driver chip is fully operational.
Innovation Solution
A signal delay circuit is integrated into the gate driver chip to delay the transmission of the gate driver signal to the scanning line, ensuring that both the gate and source driver signals arrive at the display panel simultaneously, comprising a D trigger, resistor, power supply, ground line, capacitor, and active switch, with a charging time of the capacitor longer than or equal to the display time of a frame.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate driver chip starts working normally before the source driver chip is fully operational, then the gate driver signal can be transmitted immediately, but abnormal pictures occur due to incomplete establishment of internal potential in the source driver chip
Solution Approach 1:
The patent applies preliminary action by delaying the gate driver signal transmission until the source driver chip has completed its internal potential establishment. The signal delay circuit is activated during power-on to hold the gate driver signal for a predetermined time, ensuring the source driver chip is ready before receiving the gate signal, thus preventing display abnormalities.
Solution Approach 2:
The patent introduces a signal delay circuit as an intermediary component between the gate driver chip and the scanning line. This intermediary delays the gate driver signal by a predetermined time during power-on, allowing the source driver chip to stabilize its internal potential before the gate signal is transmitted, thereby resolving the timing conflict between the two driver chips.
2Reliability
If a signal delay circuit is added to delay the gate driver signal, then the source driver chip has sufficient time to establish internal potential, but the device complexity increases
Solution Approach 1:
The patent merges the signal delay circuit directly into the gate driver chip structure, integrating the delay function within the existing gate driver architecture. This integration approach minimizes additional external components while achieving the required signal delay functionality, thus reducing the overall device complexity increase.
3Reliability
If the gate driver signal is delayed during power-on, then abnormal pictures are prevented, but the gate driver signal transmission time is extended
Solution Approach 1:
The signal delay circuit is designed to activate only during the power-on period, providing a predetermined time delay specifically when the source driver chip needs to establish its internal potential. After power-on completion, the delay function is deactivated, allowing normal fast signal transmission. This ensures the time loss is temporary and only occurs during the critical power-on phase.
Data Source
AI summary
This application discloses a display device, a driving method, and a display system. The display device includes the display panel, where the display panel includes a scanning line and a data line; a source driver chip arranged to output a source driver signal of the display panel and a gate driver chip arranged to output a gate driver signal of the display panel; a signal delay circuit, where the gate driver signal is output to the scanning line by the signal delay circuit; and the source driver signal is directly output to the data line.