Gate Driver Signal Generation for Display Refresh
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Solution Overview
Problem
The delay in turn-off time of pixel transistors in display apparatuses leads to voltage loss in pixel cells, resulting in decreased display refresh times and reduced image quality due to delayed expression of liquid crystal pixels.
Innovation Solution
A gate driver is designed with a shift register and a gate drive signal generator that includes transistors and logic circuits to generate a gate drive signal with specific voltage levels, allowing for rapid falling and rising edges to minimize voltage loss and reduce expression time of liquid crystals. This involves a level-shifting unit and logic control signal generators to manage the gate drive signal effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If the gate signal falls slowly, then the transistor remains on longer for complete liquid crystal expression, but the voltage stored in pixel cells experiences loss and display refresh time increases
Solution Approach 1:
The gate driver applies periodic voltage levels to the gate line through controlled falling edges. The gate signal transitions between different voltage states (first voltage level, second voltage level, third voltage level) in a periodic manner, allowing the transistor to turn off rapidly while still providing sufficient on-time for liquid crystal expression during each cycle.
Solution Approach 2:
The invention changes the voltage parameter of the gate signal by introducing multiple voltage levels (first, second, and third voltage levels) instead of a simple binary high/low signal. The gate signal falls from the second voltage level to the third voltage level, and the third voltage level is higher than the first voltage level, creating a controlled voltage profile that achieves fast turn-off while maintaining adequate conduction time.
2Loss of time
If the gate signal falls rapidly, then the display refresh time decreases, but the transistor turn-off may be incomplete affecting liquid crystal expression
Solution Approach 1:
The gate driver dynamically adjusts the gate signal waveform by controlling the falling edge transition from the second voltage level to the third voltage level. This dynamic voltage adjustment allows rapid signal transition for fast refresh while ensuring the transistor has adequate time in the on-state for complete liquid crystal expression, resolving the contradiction between speed and completeness.
3Device complexity
If a simple gate signal waveform is used, then the device complexity is low, but the expression time of liquid crystal pixels is delayed
Solution Approach 1:
The invention modifies the voltage parameters of the gate signal by implementing a multi-level voltage structure with first, second, and third voltage levels. This parameter change enables faster falling edges and reduced expression time without requiring complex additional circuitry, achieving improved performance with minimal increase in device complexity.
Data Source
AI summary
A gate driver is disclosed. The disclosed gate driver includes a shift register configured to generate a shift signal. The shift signal is based on a gate start signal and a gate clock signal. The gate driver further includes a gate drive signal generator configured to generate a gate drive signal. The gate drive signal is based on a gate control signal and the shift signal. The rising edge of the gate control signal precedes the falling edge of the shift signal, and the falling edge of the gate control signal follows the falling edge of the shift signal. The gate drive signal falls from a second voltage to a third voltage in response to the falling edge of the shift signal and rises from the third voltage to a first voltage in response to the falling edge of the gate control signal. The first voltage is higher than the third voltage but lower than the second voltage.