Gate Driver Stages for Display Luminance Control
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Solution Overview
Problem
Display panels experience luminance reduction due to repeated output of gate voltage during the sustain period in low-speed driving technologies, leading to image output failures.
Innovation Solution
A gate driver is designed with stages that output gate voltages using a first clock signal for writing data and a second clock signal for suppressing luminance reduction, ensuring these voltages are applied at different timings, preventing data voltage application to incorrect pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If gate voltage is repeatedly output during the sustain period to maintain luminance, then luminance reduction is suppressed, but image output failure occurs due to incorrect pixel addressing
Solution Approach 1:
The gate driver is divided into multiple stages, each responsible for specific gate lines. During the sustain period, only certain stages output gate voltage while others remain inactive, preventing incorrect pixel addressing while maintaining luminance for displayed images
Solution Approach 2:
The gate driver operates in periodic cycles with distinct writing period and sustain period. During the writing period, gate voltages are output for data writing; during the sustain period, gate voltage output is controlled selectively to maintain luminance without causing image output failures
2Use of energy by moving object
If low-speed driving technology is used to reduce power consumption, then power consumption is reduced, but luminance reduction occurs during the sustain period
Solution Approach 1:
Different stages of the gate driver are assigned different operational characteristics. During the sustain period, stages corresponding to gate lines requiring luminance maintenance are activated, while other stages remain inactive, achieving local optimization of luminance without increasing overall power consumption
Data Source
AI summary
A gate driver and a display device including the same, are discussed. The gate driver includes a plurality of stages which are dependently connected to each other. Each of the plurality of pixels includes an output unit which outputs a gate voltage by a voltage of an RQ node, a voltage of a PQ node, and a voltage of a QB node, a first controller which controls the RQ node, a second controller which controls the PQ node, and a third controller which controls the QB node. The gate voltage is configured by a first clock signal having a first phase and a second clock signal having a first phase which is different from the first phase of the first clock signal.