Gate Driver Circuit Synchronization Module for LCD Stability
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Solution Overview
Problem
Conventional single-type NMOS or PMOS gate driver circuits for liquid crystal display devices are prone to instability and failure, especially when displaying reloaded images, due to interference from the display area, leading to reliability issues in middle to large size horizontal screens.
Innovation Solution
A gate driver circuit with a synchronization module that includes forward/reverse switching and pull-up/pull-down mechanisms, utilizing N-channel metal oxide semiconductor (NMOS) thin film transistors to control the scan order and stabilize the circuit by synchronizing disturbances with a low electrical potential line, reducing the risk of reloading failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If single-type NMOS or PMOS gate driver circuits are used, then manufacturing cost is reduced and yield is improved by omitting P-doping and photomasks, but circuit stability is easily interfered by the display area especially during reloaded images
Solution Approach 1:
The patent introduces a synchronization module as an intermediary component between the shift register and the pixel array. This module includes a synchronization signal generation unit that generates synchronization signals based on clock signals, and a synchronization switch unit that uses these signals to control the timing of gate voltage application. The synchronization module acts as a mediator that coordinates the timing between different parts of the circuit, preventing instability during image reloading while maintaining the simplicity of single-type MOS structure
Solution Approach 2:
The patent implements preliminary action by pre-generating synchronization signals before the actual gate driving operation. The synchronization signal generation unit creates the necessary timing signals in advance, and the synchronization switch unit is pre-configured to activate at the correct moment. This preliminary preparation ensures that the gate driver circuit is ready to handle image reloading scenarios without causing instability, while maintaining the cost advantages of single-type MOS construction
2Productivity
If conventional GOA circuits are used, then row scanning is achieved, but circuit failure occurs easily during reloaded images especially in middle or large size horizontal screens
Solution Approach 1:
The patent incorporates feedback mechanisms through the synchronization module that continuously monitors the state of the shift register and pixel array. The synchronization signal generation unit receives clock signals and generates synchronization signals based on the actual operating state. This feedback loop allows the circuit to detect when image reloading occurs and adjust the timing accordingly, preventing circuit failure while maintaining scanning efficiency in middle to large size horizontal screens
Solution Approach 2:
The patent introduces dynamic timing adjustment through the synchronization switch unit, which can activate or deactivate based on the operational state. The synchronization signals dynamically control the gate voltage application timing, allowing the circuit to adapt to different scanning conditions including image reloading scenarios. This dynamic behavior maintains reliability across various display sizes without compromising scanning productivity
Data Source
AI summary
A gate driver circuit and a liquid crystal panel using the same are provided. The gate driver circuit includes a forward/reverse switching module, a low electrical potential line, and a synchronization module. The forward/reverse switching module includes an up to down terminal and a down to up terminal. The synchronization module is configured to electrically conduct the low electrical potential line with one of the up to down terminal and the down to up terminal which has a lower electrical potential.