Gate Driver Circuit Placement in TFT Array Substrates
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Solution Overview
Problem
Current gate driver circuit designs for liquid crystal display panels occupy a large portion of the edge region due to opaque components, hindering the achievement of lightweight and ultra-thin display products with narrow or edgeless designs, as opaque capacitors in the gate driver circuit affect transmittance and require additional space.
Innovation Solution
The integration of a gate driver circuit within pre-reserved blank regions on the TFT array substrate, utilizing top-gated thin-film transistors and a non-conducting dielectric layer to minimize interference and optimize space, allowing for a narrow edge or edgeless design by placing the gate driver circuit within the display region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the gate driver circuit is disposed at one side or both sides of the display region, then the gate driver circuit can be integrated on the array substrate, but a relatively large portion of the edge region is occupied
Solution Approach 1:
The gate driver circuit is moved from the traditional edge region (horizontal/vertical sides) into the display region, utilizing the blank regions between pixel rows or columns. This spatial reconfiguration allows the driver circuit to be integrated without occupying the edge region, thereby achieving narrow edge or edgeless display designs while maintaining circuit functionality.
2Ease of manufacture
If opaque materials are used for capacitor electrode plates in the gate driver circuit, then the circuit can be formed with conventional materials, but the transmittance of the edge region is affected
Solution Approach 1:
The gate driver circuit containing opaque capacitor structures is extracted from the edge region and relocated to the display region's blank areas. This extraction eliminates the conflict between opaque materials and light transmittance in the edge region, allowing conventional opaque materials to be used for capacitors while maintaining high transmittance in the original edge region.
3Area of moving object
If the gate driver circuit is disposed in the non-display region, then the display region can be maximized, but a larger space is occupied and narrow edge design becomes difficult
Solution Approach 1:
Instead of placing the gate driver circuit in the non-display region (traditional approach) or occupying the edge region, the circuit is positioned within the display region's blank regions (between pixel rows/columns). This innovative spatial arrangement allows the display region to be maximized while the driver circuit occupies only the previously unused blank spaces, achieving both goals simultaneously.
Data Source
AI summary
A thin-film transistor (TFT) array substrate is provided. The thin-film transistor (TFT) array substrate comprises a substrate having at least a display region; and a plurality of top-gated thin-film transistors formed over the substrate. The thin-film transistor (TFT) array substrate also comprises a plurality of scan lines and a plurality of data lines formed over the substrate in the display region and defining a plurality of sub-pixels, wherein a plurality of pre-reserved blank regions are configured among the scan lines, the data lines, and the plurality of sub-pixels in the display region; and a gate driver circuit formed over the substrate in the display region and disposed in the pre-reserved blank regions in the display region.