Gate Driver Circuit Integration in Thin-Film Transistor Array Substrates
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Solution Overview
Problem
Current gate driver circuit designs for display panels occupy a large edge region due to opaque capacitors and devices, making it difficult to achieve a narrow or edgeless design, and the opaque nature affects transmittance and curing of frame sealants during packaging.
Innovation Solution
The integration of a gate driver circuit within pre-reserved blank regions on the TFT array substrate, using bottom-gated thin-film transistors and capacitors, allows for a more compact design by placing the gate driver circuit in the display region, reducing the need for non-display region space and minimizing interference with the display.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate driver circuit is disposed in the non-display region using conventional opaque capacitors, then the circuit functionality is achieved, but the edge region space is excessively occupied and transmittance is reduced
Solution Approach 1:
The gate driver circuit is merged with the display region by integrating it into the pixel structure. The capacitor is formed using the pixel electrode and common electrode that already exist in the display region, eliminating the need for separate capacitor structures in the non-display region. This merging allows the gate driver circuit to function within the display region without occupying additional edge space.
Solution Approach 2:
The capacitor structure transitions from a conventional planar structure in the non-display region to a vertical/stacked structure within the pixel region. By utilizing the pixel electrode and common electrode in different layers, the capacitor is formed in the vertical dimension rather than occupying horizontal edge space, thus achieving circuit functionality without increasing the edge region footprint.
2Reliability
If opaque capacitor structures are used in the gate driver circuit, then the circuit components are well-defined, but the transmittance of the edge region is affected and frame sealant curing is incomplete
Solution Approach 1:
The capacitor structure changes from opaque to transparent by utilizing the pixel electrode and common electrode materials that are inherently transparent. This material selection change allows ultraviolet light to pass through the capacitor region during frame sealant curing, ensuring complete curing while maintaining the structural definition of the capacitor.
Solution Approach 2:
The pixel electrode and common electrode serve as intermediaries that fulfill both the electrical function of the capacitor and the optical function of allowing UV light transmission. These intermediary structures enable the capacitor to perform its electrical storage function while simultaneously allowing the ultraviolet curing light to pass through without being blocked by opaque materials.
3Area of stationary object
If the gate driver circuit is integrated in the display region, then the edge region space is minimized, but the layout complexity increases
Solution Approach 1:
The pixel electrode and common electrode serve multiple functions: they define the pixel structure for display purposes, provide the capacitor electrodes for gate driver circuit functionality, and allow UV light transmission for curing. This multi-functionality reduces layout complexity by eliminating the need for separate dedicated capacitor structures and simplifies the overall design by using existing structures for multiple purposes.
Data Source
AI summary
A thin-film transistor (TFT) array substrate is provided. The thin-film transistor (TFT) array substrate comprises a substrate having at least a display region; and a plurality of bottom-gated thin-film transistors formed over the substrate. The thin-film transistor (TFT) array substrate also includes a plurality of scan lines and a plurality of data lines formed over the substrate in the display region and defining a plurality of sub-pixels, wherein a plurality pre-reserved blank regions are configured among the scan lines, the data lines and the plurality of sub-pixels; and a gate driver circuit formed over the substrate in the display region and disposed in the pre-reserved blank regions in the display region.