Gate Driver Circuit Stability Against Threshold Voltage Shifts
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Solution Overview
Problem
Existing display apparatuses face instability issues due to the increase in threshold voltages of transistors and driving transistors during the power-on period, affecting the generation of pulse signals for scan lines.
Innovation Solution
A gate driver with unit circuits that include an output terminal, an input transistor, an output transistor, and a holding module, where the output transistor generates shifted pulse signals synchronous with the clock control signal, and the holding module controls the output during initial and operation periods using trigger, first, and second control signals to manage voltage levels effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high level voltage is provided to the gate driver during power-on period to initialize the circuit, then the transistors and driving transistor are turned on, but the threshold voltages of the transistor and driving transistor increase, causing instability in the display apparatus
Solution Approach 1:
The gate driver is divided into multiple unit circuits (first unit circuit, second unit circuit, third unit circuit, etc.) connected in series. Each unit circuit independently processes clock signals and generates pulse signals for specific scan lines. This segmentation isolates the threshold voltage increase effect to individual unit circuits, preventing system-wide instability while maintaining overall functionality.
Solution Approach 2:
Capacitors are introduced as intermediary elements to store and transfer voltage levels between unit circuits. The capacitor in each unit circuit maintains the necessary voltage level for the driving transistor to operate correctly, compensating for threshold voltage increases and ensuring stable pulse signal generation despite the harmful effect.
2Productivity
If multiple unit circuits are connected in series to generate shifted pulse signals for multiple scan lines, then the scanning function is achieved, but the circuit complexity increases with more transistors and capacitors in each unit circuit
Solution Approach 1:
Each unit circuit is designed with identical internal structure and functionality, capable of receiving clock signals, generating pulse signals, and driving specific scan lines. This universal design allows the same circuit block to be replicated multiple times, simplifying the overall system architecture while maintaining high productivity through parallel pulse signal generation across multiple scan lines.
Solution Approach 2:
The unit circuits are connected in a nested series configuration where the output of one unit circuit feeds into the next, creating a cascaded structure. This nesting allows compact arrangement of multiple functional units while maintaining clear signal flow and control, reducing spatial complexity despite the increased number of components.
3Measurement precision
If the clock signals are provided continuously to all unit circuits, then the pulse signals are generated synchronously, but the timing precision is affected by threshold voltage variations during power-on period
Solution Approach 1:
The capacitors in each unit circuit are pre-charged to appropriate voltage levels before the unit circuits begin operating. This preliminary action ensures that when the clock signals are applied, the driving transistors have sufficient voltage headroom to operate correctly despite threshold voltage increases, maintaining precise timing of pulse signal generation from the first clock cycle.
Solution Approach 2:
The output of each unit circuit is fed back to influence the operation of subsequent unit circuits in the series. This feedback mechanism allows each stage to adapt to threshold voltage variations, maintaining synchronous operation and timing precision across all unit circuits even when individual transistor characteristics vary during power-on period.
Data Source
AI summary
A gate driver with reduced voltage fluctuations driving a display device generates pulse signals shifted in a specified phase. The gate driver includes connected unit circuits. Each unit circuit includes an output terminal, input and output transistors, and a holding module. First and second control signals, alternating oppositely between high and low states, govern the two transistors. The input transistor is controlled by a first control signal and outputs a high level voltage to a first node based on a trigger signal. The output transistor outputs the shifted pulse signal synchronously with a clock control signal, based on the high level voltage of the first node. Initially, the trigger signal is low and the first and second control signals are high. The holding module outputs the low level voltage to the output terminal based on the first control signal and the second control signal.