Dual Gate Driver Timing for Low-Distortion Gate Signal Lines
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Solution Overview
Problem
Existing semiconductor devices with separated gate driver circuits experience signal delay, distortion, and transistor deterioration due to uneven signal output and non-uniform potential changes on gate signal lines.
Innovation Solution
A semiconductor device design where both gate driver circuits output selection signals during selection periods and one outputs non-selection signals during non-selection periods, with one circuit turning off during non-selection to reduce signal delay and transistor deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If gate driver circuits are separated into right and left in the pixel portion, then the pixel portion can be controlled more effectively, but signal delay and distortion occur due to uneven signal output
Solution Approach 1:
The gate driver circuit is divided into first and second gate driver circuits positioned in left and right peripheral regions, respectively. Each circuit drives gate lines in its respective region, enabling distributed control that reduces signal delay and distortion while maintaining effective control over the pixel portion.
Solution Approach 2:
The first gate driver circuit outputs selection signals to odd-numbered gate lines in the left peripheral region, while the second gate driver circuit outputs selection signals to even-numbered gate lines in the right peripheral region. This local differentiation ensures that each circuit optimizes signal output for its specific region, reducing overall signal distortion.
2Duration of action of moving object
If gate driver circuits output signals continuously, then signal output is maintained, but transistor deterioration occurs
Solution Approach 1:
The gate driver circuits operate in periodic cycles where one circuit outputs selection signals while the other outputs non-selection signals. During non-selection periods, transistors in the inactive circuit are turned off, preventing deterioration. This periodic operation pattern allows continuous signal output while protecting transistors from prolonged activation.
Solution Approach 2:
During non-selection periods, the inactive gate driver circuit turns off its transistors, effectively discarding their active state. This allows the transistors to recover from continuous operation stress, reducing deterioration and extending their operational lifespan while maintaining signal output capability.
Data Source
AI summary
A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.