Gate Driver Timing Offset for Display Resolution
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Solution Overview
Problem
Gate doubling driving in display devices leads to reduced vertical resolution, causing aliasing and deterioration of image quality, particularly affecting the smoothness of image edges and shapes with curved lines or oblique angles.
Innovation Solution
A method that compresses and processes image data to generate output data with concurrent gate-on voltage pulses applied to neighboring gate lines, with varying starting times and overlapping pulses to reduce aliasing and enhance resolution, allowing for smoother image edges and improved image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate doubling driving is used to increase frame rate and reduce crosstalk, then response speed is improved and crosstalk is reduced, but vertical resolution deteriorates causing aliasing
Solution Approach 1:
The gate lines are divided into multiple groups, with each group containing k neighboring gate lines. Within each group, gate-on voltage pulses are applied concurrently to multiple gate lines simultaneously, while between groups the pulses are applied sequentially. This segmentation allows partial parallel processing (improving speed) while maintaining structured control (preserving resolution through selective timing offsets).
Solution Approach 2:
The starting times of gate-on voltage pulses are dynamically adjusted based on the group index. Each group is assigned a different starting time offset, creating a dynamic timing pattern that varies across gate line groups. This dynamic approach allows the system to optimize both concurrent driving (for speed) and sequential control (for resolution) by adapting pulse timing to the specific group being driven.
2Productivity
If gate doubling outputs compressed image data to increase frame rate, then productivity is improved, but vertical resolution is reduced causing aliasing
Solution Approach 1:
Image data processing is segmented by gate line groups. Each group of k gate lines receives processed image data with timing offsets specific to that group. This segmentation allows the system to process compressed image data at high frame rates while maintaining vertical resolution through group-specific timing control that prevents aliasing artifacts.
Solution Approach 2:
The gate-on voltage pulses are applied in periodic cycles, with each cycle processing one group of k gate lines. The periodic timing pattern, with consistent offsets between groups, enables systematic processing of compressed image data while maintaining the temporal structure necessary for preserving vertical resolution despite compression.
Data Source
AI summary
A display device includes gate lines, data lines, pixels connected to the gate lines and data lines, a data driver, a gate driver, and a signal controller for controlling the data driver and gate driver. A method for driving the display device includes: compressing, by the signal controller, vertical resolution of input image data of each frame by k or receiving by the signal controller the compressed input image data; processing by the signal controller the compressed input image data to generate output image data; generating, by the data driver, data voltages based on the output image data and applying the data voltages to the data lines; and applying, by the gate driver, gate-on voltage pulses concurrently to k neighboring gate lines corresponding to the applied data voltages. Starting times of the gate-on voltage pulses of at least two of the k neighboring gate lines are different from each other.