Gate Driver Timing Synchronization for Stable DC-DC Converters
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Solution Overview
Problem
In DC-to-DC converters, synchronizing timing signals across multiple gate drivers is challenging due to non-zero bond wire inductance, leading to instability and potential run-away conditions, especially during low duty-cycle operations.
Innovation Solution
A circuit is provided to synchronize timing signals across multiple gate drivers by ensuring that like edges of the timing signals coincide, using path length matching and variable delay lines to account for propagation delays, and allowing for a selectable number of synchronized timing signals responsive to control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If timing signals are provided to multiple gate drivers without synchronization, then the converter can operate with simple circuitry, but instability and run-away conditions occur due to non-zero bond wire inductance and propagation delays
Solution Approach 1:
The patent applies preliminary action by pre-synchronizing timing signals before distributing them to multiple gate drivers. A timing signal generator produces synchronized timing signals that account for propagation delays and bond wire inductance in advance, ensuring all gate drivers receive precisely timed signals simultaneously. This prevents instability and run-away conditions during low duty-cycle operations without requiring complex feedback mechanisms.
Solution Approach 2:
The patent uses an intermediary approach by introducing a dedicated timing signal generator circuit as a mediator between the control logic and multiple gate drivers. This intermediary component actively manages and synchronizes timing signals, compensating for propagation delays and bond wire inductance effects, thereby ensuring stable converter operation while maintaining circuit modularity and manageability.
2Reliability
If path length matching is used to synchronize timing signals, then simultaneous current delivery to gate drivers is achieved, but circuit design and manufacturing precision requirements increase
Solution Approach 1:
The patent applies parameter changes by deliberately introducing variable delay elements into the timing signal paths. Instead of relying solely on precise physical path length matching, the circuit dynamically adjusts signal propagation parameters using controllable delay circuits. This allows compensation for manufacturing tolerances and ensures timing synchronization across all gate drivers regardless of minor variations in trace lengths or bond wire characteristics.
3Power
If multiple gate drivers are used to handle higher current, then the converter power capacity increases, but timing synchronization becomes more difficult due to accumulated propagation delays
Solution Approach 1:
The patent applies segmentation by dividing the timing signal generation function into multiple independent but synchronized sources. Each gate driver receives timing signals from its own dedicated timing signal generator channel, allowing individual optimization and compensation for each path. This segmented approach scales efficiently to support higher power converters with more gate drivers while maintaining timing synchronization through independent delay compensation in each segment.
Data Source
AI summary
One or more examples relate, generally, to providing timing signals to gate drivers of a converter. An example apparatus for providing timing signals to gate drivers of a converter includes a circuit that includes a timing input, and a plurality of outputs. The timing input may receive an incoming timing signal. The plurality of outputs may couple to a respective plurality of gate drivers to control an output voltage of a converter. The circuit may provide respective timing signals, at respective ones of the plurality of outputs at least partially responsive to the incoming timing signal, the respective timing signals synchronized such that like edges of the respective timing signals coincide.