Gate Driver Circuit Variable Clock Cycle Control
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Solution Overview
Problem
Existing gate driver ICs are not versatile enough to accommodate varying numbers and arrangements of gate signal lines and different specifications of image display apparatus, requiring dedicated designs that are costly and time-consuming to develop.
Innovation Solution
A gate driver circuit that includes a setting circuit to switch between two modes, allowing for synchronization with either one clock cycle or multiple clock cycles, enabling the same IC to be used across different configurations by adjusting the output voltage based on data position, thereby supporting both high and low slew rate requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate driver IC is designed for a specific configuration of gate signal lines, then it can meet the specific slew rate and load capacity requirements, but it cannot be used for other configurations, requiring dedicated designs for each application
Solution Approach 1:
The patent implements dynamic clock cycle control where the clock cycle period is variable rather than fixed. The gate driver circuit can adjust the clock cycle to be equal to or longer than a reference period, allowing the same IC to adapt to different gate signal line configurations and load capacities while maintaining reliable operation. This dynamic adjustment enables a single IC design to serve multiple applications with different slew rate requirements.
Solution Approach 2:
The patent changes the time parameter (clock cycle period) as a variable control parameter. By making the clock cycle period adjustable rather than fixed, the gate driver IC can modify its operating characteristics to match different gate signal line configurations. This parameter change approach allows the same hardware design to accommodate varying slew rate requirements and load capacities across different display apparatus specifications.
2Reliability
If different gate driver ICs are designed for different image display apparatus specifications, then each apparatus gets optimized performance, but development costs and time increase significantly
Solution Approach 1:
The patent creates a universal gate driver IC design that can function with multiple gate signal line configurations through variable clock cycle control. A single IC design serves multiple functions by adjusting its clock period, eliminating the need to develop separate dedicated ICs for each display apparatus specification. This multi-functionality approach maintains performance optimization while reducing development overhead.
Solution Approach 2:
The dynamic clock cycle adjustment capability allows one gate driver IC design to adapt to various display apparatus specifications without requiring multiple dedicated designs. This reduces development time and costs while maintaining optimized performance for each application through software or control-based configuration rather than hardware redesign.
3Device complexity
If the clock cycle is fixed at a reference period, then the circuit operation is simplified, but it cannot accommodate configurations requiring longer time periods for proper signal propagation
Solution Approach 1:
The patent implements a dynamic clock cycle control mechanism where the clock period can be adjusted to be equal to or longer than a reference period. This maintains relatively simple circuit operation while adding the flexibility to accommodate different time requirements for signal propagation across various gate signal line configurations. The dynamic adjustment is achieved through control logic that modifies the clock timing based on configuration requirements.
Data Source
AI summary
A gate driver IC (i.e., gate driver circuit), when set to a first mode by a logic signal of the terminal FNC*, shifts data in the gate driver IC in synchronization with one clock cycle of a clock inputted to the terminal CLK** (clock input terminal), and outputs a selection voltage or a non-selection voltage based on a data position in the gate driver IC; and when set to a second mode by a logic signal of the terminal FNC*, shifts data in the gate driver IC in synchronization with n clock cycles (n is an integer of at least 2) of a clock inputted to the terminal CLK**, and outputs the selection voltage or the non-selection voltage based on the data position in the gate driver IC.