Gate Driver Circuit Voltage Adjustment for Leakage Reduction

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Solution Overview

Problem

The existing gate driver circuits in display devices have a large size due to the high number of transistors and lines, leading to increased leakage current and deteriorated image quality, as well as reduced transistor lifespan due to voltage stress.

Innovation Solution

A gate driver circuit design with reduced transistors and lines, incorporating a configuration with M, Q, QH, and QB nodes, and a voltage adjustment mechanism to minimize voltage stress on transistors, thereby reducing the circuit size and improving durability and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the number of transistors in each stage circuit is reduced to decrease gate driver circuit size, then the display area increases, but leakage current increases and image quality deteriorates

Engineering Contradiction:
Improvedisplay areaVSAvoidimage quality
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent introduces a voltage adjustment mechanism that dynamically changes the voltage level at the control node based on the operational state of the transistor. When the transistor is in the off-state, the voltage is adjusted to a level that ensures complete turn-off and prevents leakage current, thereby maintaining image quality even with reduced transistor count in the gate driver circuit.

Inventive Principle:
Principle #35Parameter changes

2Area of stationary object

If the number of transistors in each stage circuit is reduced to decrease gate driver circuit size, then the gate driver circuit size decreases, but leakage current occurs due to threshold voltage changes

Engineering Contradiction:
Improvegate driver circuit sizeVSAvoidleakage current
Core Design Contradiction:
Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The patent applies preliminary anti-action by anticipating the threshold voltage changes that occur during transistor operation and preemptively adjusting the control node voltage to counteract these changes. This prevents leakage current from occurring in the first place, rather than attempting to correct it after the fact.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The voltage adjustment mechanism dynamically modifies the control node voltage parameter based on the transistor's operational state, ensuring that the transistor remains completely turned off during non-conduction periods and preventing leakage current generation.

Inventive Principle:
Principle #35Parameter changes

3Area of stationary object

If the number of transistors in each stage circuit is reduced to decrease gate driver circuit size, then the gate driver circuit size decreases, but transistor lifespan decreases due to voltage stress

Engineering Contradiction:
Improvegate driver circuit sizeVSAvoidtransistor lifespan
Core Design Contradiction:
Area of stationary objectVSDuration of action of stationary object

Solution Approach 1:

The patent implements a voltage adjustment mechanism that modifies the voltage parameter at the control node based on the operational state of the transistor. By adjusting the voltage to appropriate levels during different operational phases, the mechanism reduces voltage stress on the transistor, thereby extending its lifespan while maintaining the reduced gate driver circuit size.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11574598B2Gate driver circuit and display device including the same
Publication Date: 2023.02.07 LG DISPLAY CO LTD
  • US11574598B2 patent drawing
  • US11574598B2 patent drawing
  • US11574598B2 patent drawing

AI summary

Disclosed are a gate driver circuit having a reduced size, and a display device including the same. The gate driver circuit includes a plurality of stage circuits. Each stage circuit supplies a gate signal to each of gate lines arranged in a display panel, and includes a M node, a Q node, a QH node, and a QB node. Each stage circuit includes a gate signal output module configured to operate based on a voltage level of the Q node or a voltage level of the QB node to output first to j-th gate signals based on first to j-th scan clock signals or a first low-potential voltage.