Gate Driver Voltage Control for Single-Step Display Scanning
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Solution Overview
Problem
Existing gate drivers in display devices experience issues with PMOS and NMOS transistors not turning on sufficiently due to improper voltage levels at internal nodes, leading to gate signals falling or rising in two steps, which results in visible horizontal lines on the display.
Innovation Solution
A gate driver design incorporating an input circuit, level control circuit, pull down circuit, and voltage output circuit, utilizing PMOS and NMOS transistors and capacitors to control voltage levels at internal nodes, ensuring the gate signal transitions in one step by boosting or maintaining appropriate voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the voltage level of the internal node is not properly controlled, then the circuit structure is simple, but the PMOS transistor cannot be sufficiently turned on, causing the gate signal to fall in two steps and producing horizontal lines on the display
Solution Approach 1:
The patent introduces an internal node as an intermediary between the input signal and the PMOS transistor gate. This internal node allows for voltage level control through capacitive coupling, enabling the PMOS transistor to be properly turned on without directly modifying the input signal path. The intermediary node resolves the contradiction by providing a buffer that can be controlled to achieve smooth gate signal transitions.
Solution Approach 2:
The patent changes the voltage parameter of the internal node through capacitive coupling from the clock signal. By controlling the voltage level at the internal node, the gate voltage of the PMOS transistor is adjusted to ensure proper turning on. This parameter change approach maintains circuit simplicity while achieving reliable gate signal transitions without horizontal lines.
2Reliability
If the voltage level of the internal node is not properly controlled, then the circuit structure is simple, but the NMOS transistor cannot be sufficiently turned on, causing the gate signal to rise in two steps and producing horizontal lines on the display
Solution Approach 1:
The internal node serves as an intermediary that controls the voltage level for the NMOS transistor gate through capacitive coupling. This intermediary mechanism enables proper NMOS transistor turning on by adjusting the internal node voltage, thereby achieving smooth gate signal rising edges without horizontal lines while keeping the overall circuit structure relatively simple.
Solution Approach 2:
The voltage parameter of the internal node is dynamically changed through capacitive coupling to ensure the NMOS transistor receives the appropriate gate voltage for sufficient turning on. This parameter control approach resolves the contradiction by enabling smooth gate signal transitions without requiring complex additional circuitry.
3Reliability
If the internal node voltage is not controlled, then the circuit is simple, but the gate signal transitions in two steps causing visible horizontal lines
Solution Approach 1:
The internal node acts as a voltage control intermediary that mediates between the clock signal and the transistor gates. Through capacitive coupling, it translates the clock signal voltage changes into appropriate gate voltage levels for both PMOS and NMOS transistors, ensuring single-step transitions and eliminating horizontal lines without requiring complex voltage control circuits.
Solution Approach 2:
The internal node performs multiple functions: it controls both PMOS and NMOS transistor gate voltages, couples the clock signal to the transistor gates, and ensures proper turning on/off timing for both transistors. This multi-functional approach achieves reliable display quality while minimizing circuit complexity by using a single control node for multiple purposes.
Data Source
AI summary
A gate driver includes an input circuit, a level control circuit, a pull down circuit, and a voltage output circuit. The level control circuit includes a first p-type metal-oxide-semiconductor (PMOS) transistor including a gate electrode connected to a first control node, a first electrode receiving a clock signal, and a second electrode, a first capacitor including a first electrode connected to the second electrode of the first PMOS transistor and a second electrode connected to the first control node, and a first NMOS transistor including a gate electrode receiving a low gate voltage, a first electrode connected to the first control node, and a second electrode connected to a second control node.