Gate Driver Transistor Circuit for Threshold Voltage Stability
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Solution Overview
Problem
The threshold voltage shift of transistors in gate drivers can lead to reliability issues, resulting in decreased performance and increased leakage currents, which affects the overall reliability and display quality of display devices.
Innovation Solution
A gate driver design that includes specific transistor configurations and voltage levels, such as the use of NMOS and PMOS transistors with varying gate voltage levels, coupled with capacitors to manage threshold voltage shifts, ensuring a sufficient negative margin and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistor configurations are used in gate drivers, then device complexity is reduced, but threshold voltage shift occurs leading to reliability degradation
Solution Approach 1:
The gate driver is divided into multiple stages (first stage, second stage, third stage) with distinct transistor configurations. Each stage handles specific voltage levels and signal transitions, allowing threshold voltage shifts to be managed locally without affecting the entire circuit. The segmentation enables independent optimization of each stage for reliability while maintaining overall system manageability.
Solution Approach 2:
Different transistor configurations are applied to different parts of the gate driver circuit based on their specific functional requirements. The first transistor uses one configuration optimized for initial signal transmission, while the third transistor uses a different configuration optimized for maintaining voltage margins. This local quality approach ensures that each transistor operates in its optimal performance regime, improving overall reliability without requiring complete circuit redesign.
2Reliability
If higher power voltage levels are used to compensate for threshold voltage shifts, then reliability is improved, but power consumption increases
Solution Approach 1:
The gate driver dynamically adjusts voltage levels based on operational requirements. The third transistor outputs different voltage levels (second low gate voltage or high gate voltage) depending on the input signal state. This dynamic voltage adjustment maintains sufficient negative margins during critical operations while reducing power consumption during normal operation, rather than continuously operating at maximum voltage levels.
Solution Approach 2:
The circuit changes voltage parameters adaptively - using a power voltage higher than the second low gate voltage specifically for the third transistor's source terminal to ensure adequate negative margin, while other parts of the circuit operate at lower voltage levels. This selective parameter change optimizes the balance between reliability and power consumption by applying higher voltages only where and when needed.
3Reliability
If threshold voltage shift margin is not sufficiently secured, then device complexity is reduced, but leakage currents increase affecting reliability
Solution Approach 1:
The third transistor acts as an intermediary element that receives a power voltage (higher than second low gate voltage) at its source terminal and conditions it appropriately for output. This intermediary transistor buffers and regulates voltage levels, preventing direct exposure of other circuit elements to high voltage variations that would cause leakage currents, while maintaining adequate negative margins for reliability.
Data Source
AI summary
A gate driver includes: a first transistor configured to transmit an input signal to a control node; a third transistor including a gate connected to the control node, a first terminal configured to receive a power voltage having a level higher than a level of a second low gate voltage, and a second terminal connected to an inverting control node; a fifth transistor configured to output the second low gate voltage as a gate signal in response to a signal of the control node; and a sixth transistor configured to output a high gate voltage as the gate signal in response to a signal of the inverting control node.