Gate Driver Well-Bias Clamping for Latchup Prevention

The patent combines the well bias voltage clamping function with the existing gate driver circuit by integrating a clamp transistor whose source is connected to the P-well and whose gate is controlled by the gate driver output. This merging approach allows the clamping function to be implemented without adding a completely separate control circuit, thereby improving reliability while minimizing the increase in device complexity.

The clamp transistor is configured to automatically activate when voltage differentials exceed breakdown limits. The transistor's gate is driven by the gate driver output signal, and when this signal creates a voltage differential that would cause latchup or junction breakdown, the transistor automatically turns on to clamp the well bias voltage and prevent the harmful effect, without requiring external intervention or additional control logic.

The voltage clamping function is merged with the gate driver circuitry by using the gate driver output to control the clamp transistor. This integration allows the clamping function to be achieved without adding a separate voltage control circuit that would occupy additional semiconductor area. The clamp transistor shares the gate driver output connection, thereby maintaining voltage stability while minimizing area overhead.

The patent applies voltage clamping locally at the P-well region where it is most needed to prevent latchup and junction breakdown. Rather than implementing a global voltage control system, the solution focuses on the specific location (P-well) where voltage differentials cause problems, using a single clamp transistor positioned strategically to provide local protection. This localized approach achieves stability improvement with minimal semiconductor area consumption.

The clamp transistor operates in a periodic or event-driven manner rather than continuously. It remains off during normal operation and only activates when the gate driver output signal creates a voltage differential that would cause latchup or junction breakdown. This periodic activation pattern, triggered by specific voltage conditions, maintains reliability by preventing parasitic transistor activation while minimizing power consumption by keeping the transistor off during normal operation.

The clamp transistor is configured to automatically activate only when needed, based on the voltage conditions created by the gate driver output signal. When the gate driver output creates a voltage differential that would cause latchup or junction breakdown, the transistor self-activates to clamp the well bias voltage. During normal operation, the transistor remains off and consumes minimal power. This self-service mechanism ensures reliability improvement without continuous power consumption.