Gate Driver Wiring Layout for Parasitic Capacitance Reduction
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Solution Overview
Problem
In display devices, the overlap of signal transferring wirings for gate drivers leads to the formation of parasitic capacitors, increasing power consumption and heat generation due to the increased load on these wirings.
Innovation Solution
The layout of the gate driver and signal transferring wirings is optimized by positioning the clock signal wiring on one side and the voltage wiring on the opposite side, with the voltage wiring comprising main and sub lines of different materials, and using contact holes to connect them, thereby reducing overlapping and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If signal transferring wirings are arranged to connect gate driver stages, then the gate driver can function properly, but parasitic capacitors are formed at crossing portions increasing power consumption
Solution Approach 1:
The signal transferring wirings are segmented into separate regions: clock signal wirings are positioned in a first region while voltage wirings are positioned in a second region. This spatial segmentation prevents overlapping and crossing between different signal types, eliminating parasitic capacitor formation while maintaining proper gate driver functionality through dedicated signal paths.
2Adaptability or versatility
If signal transferring wirings cross each other to reach different gate driver stages, then comprehensive signal distribution is achieved, but load on wirings increases due to parasitic capacitance
Solution Approach 1:
The wiring layout transitions from a two-dimensional planar arrangement with crossings to a three-dimensional organized structure using distinct regions and layers. Clock signal wirings and voltage wirings are assigned to different spatial regions, allowing comprehensive signal distribution across gate driver stages without wiring crossings, thereby eliminating parasitic capacitance and reducing energy loss.
3Productivity
If wirings are positioned to transfer multiple signals across the gate driver, then signal transferring capability is improved, but heat generation increases due to increased load
Solution Approach 1:
Different signal types are extracted and separated into dedicated wiring regions: clock signals are transferred through clock signal wirings in a first region, while voltage signals are transferred through voltage wirings in a second region. This extraction and separation eliminates unnecessary wiring crossings and parasitic capacitance, maintaining high signal transferring capability while reducing heat generation from excessive load.
Data Source
AI summary
Provided is a display device, more particularly, a display device including a gate driver. The display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; a gate driver including a plurality of stages outputting gate signals to the plurality of gate lines; a clock signal wiring transferring a clock signal to the gate driver; a voltage wiring transferring an off voltage to the gate driver, in which the clock signal wiring is positioned at a first side of the gate driver, and the voltage wiring is positioned at a second side facing the first side of the gate driver.