Gate Driver Wiring Reduces Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional display devices experience increased power consumption and malfunction due to parasitic capacitance and erosion at contact electrodes in gate drivers, which are formed on the display panel with multiple contact electrodes.
Innovation Solution
A driving unit with a reduced number of contact electrodes is designed, where the first and second clock wirings connect alternately with stages, and third and fourth connecting wirings connect the first and second clock wirings with the circuit stages, reducing parasitic capacitance and contact electrode erosion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple contact electrodes are used to connect clock wirings with circuit stages, then electrical connection is achieved, but contact electrode erosion occurs causing malfunction
Solution Approach 1:
The patent extracts the harmful function of direct contact between clock wirings and circuit stages by introducing intermediate connecting wirings. These connecting wirings act as buffer elements that eliminate direct contact erosion while maintaining electrical connection, thereby solving the malfunction issue caused by contact electrode erosion.
Solution Approach 2:
The patent introduces connecting wirings as intermediary elements between the clock wirings and circuit stages. These intermediaries reduce the direct interaction between high-voltage clock signals and contact electrodes, preventing erosion and improving reliability without compromising the electrical connection function.
2Reliability
If connecting wirings are formed on different layers from clock wirings, then electrical connection is achieved, but parasitic capacitance increases causing power consumption increase
Solution Approach 1:
The patent transitions from a planar connection approach to a three-dimensional layered structure. By forming connecting wirings on different layers from clock wirings and using vertical connections, the patent reduces parasitic capacitance between signal lines while maintaining reliable electrical connection, thereby reducing power consumption.
Solution Approach 2:
The patent segments the electrical connection path into multiple stages: clock wirings on one layer, connecting wirings on intermediate layers, and circuit stages on other layers. This segmentation allows optimization of each segment's function, reducing parasitic capacitance effects while maintaining connection reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces power consumption and prevents gate driver malfunction by minimizing parasitic capacitance and contact electrode erosion, enhancing the reliability and efficiency of the display device.
Implementation Method 1
This configuration causes parasitic capacitances between the connecting wirings CL and the vertical synchronization start signal wiring STVL, the clock wiring CKVL, the clock-bar wiring CKVBL, and the off voltage wiring VoffL, respectively
Data Source
AI summary
A gate driver includes multiple stages. Each stage has a circuit portion and a wiring portion. The wiring portion delivers first and second clock signals to the circuit portion. Further, the wiring portion includes first and second clock wirings receiving the first and second clock signal, respectively, first connecting wirings electrically connecting the first clock wiring with a first every other stage, and second connecting wirings electrically connecting the second clock wiring with the odd-numbered stages. Further, the wiring portion includes third connecting wirings electrically connecting the first connecting wiring with a second every other stage and fourth connecting wirings electrically connecting the second connecting wiring with the even-numbered stages. This configuration may prevent the gate driver from operating erroneously and reduce power consumed by the gate driver.