Gate Driving Circuit with Asymmetric Shift Registers
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Solution Overview
Problem
Planar display devices face challenges in maintaining image display quality while reducing production costs and bezel widths, as shift registers fabricated on active array substrates increase device area and power consumption.
Innovation Solution
A gate driving circuit comprising a first and second gate driving circuit with varying numbers of transistors and widths, allowing for reduced border width and increased layout area, while effectively reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If shift registers are fabricated onto the active array substrate, then production cost is reduced, but device area increases
Solution Approach 1:
The gate driving circuit is divided into two separate gate driving circuits, each responsible for driving different sets of scan lines. This segmentation allows the circuits to be distributed across the substrate, reducing the concentration of circuit area in one location and enabling more efficient space utilization in the display device.
Solution Approach 2:
The patent utilizes the peripheral area of the display substrate by placing gate driving circuits in the border regions. This dimensional arrangement allows the driving circuits to be integrated without significantly increasing the active display area, effectively using otherwise wasted space.
2Ease of manufacture
If shift registers are fabricated onto the active array substrate, then production cost is reduced, but power consumption increases
Solution Approach 1:
By dividing the gate driving function into two separate gate driving circuits, each circuit drives a subset of scan lines. This segmentation reduces the power consumption of each individual circuit compared to a single circuit driving all scan lines, while maintaining the cost advantage of integrated fabrication.
Solution Approach 2:
The two gate driving circuits operate in an alternating or coordinated manner to drive different sets of scan lines during different time periods. This periodic operation distributes the power consumption over time, reducing peak power requirements and overall energy consumption compared to a single continuous driving circuit.
3Area of stationary object
If border width is reduced, then layout area for other circuits is increased, but circuit design complexity increases
Solution Approach 1:
The gate driving circuit is segmented into two independent gate driving circuits, each with its own shift registers and driving logic. This segmentation simplifies the design of each individual circuit by reducing the number of scan lines each must handle, while the overall system achieves the desired border width reduction through coordinated operation of both circuits.
Solution Approach 2:
The patent rearranges the circuit layout by placing gate driving circuits in the peripheral border regions rather than concentrating them in the center. This spatial reorganization reduces the impact on the active display area and provides more layout area for other circuits, while the border width is managed through the distributed arrangement of the two gate driving circuits.
Data Source
AI summary
A gate driving circuit includes a first gate driving circuit and a second gate driving circuit. The first driving circuit includes 1st to Nth first shift registers that are configured to output 1st to Nth first scan signals to N number of scan lines, respectively. The second driving circuit includes 1st to Nth second shift registers that are configured to output 1st to Nth second scan signals to the other N number of scan lines, respectively. The number of transistors in each of the 1st to Nth second shift registers is less than the number of transistors in each of the 1st to Nth first shift registers.