Gate Driving Device Blank Period Voltage Control
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Solution Overview
Problem
Conventional gate driving devices in display panels experience voltage level increases due to charge sharing between gate-on and gate-off voltages during blank periods, leading to display defects.
Innovation Solution
A gate driving device that includes a gate controller capable of generating gate clock signals at a gate-off voltage level when specific control signals are at a low level, preventing voltage level increases and integrating a detection circuit to identify blank periods or fail modes to adjust gate clock signals accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate controller generates gate clock signals during blank periods, then the gate driving device can maintain continuous operation, but voltage level increases occur due to charge sharing between gate-on and gate-off voltages causing display defects
Solution Approach 1:
The detection circuit detects the blank period in advance and the gate controller preemptively stops generating gate clock signals before the voltage level can increase due to charge sharing. This preliminary action prevents the harmful voltage increase from occurring in the first place, thereby maintaining display quality without defects.
2Ease of manufacture
If the gate driving device integrates the gate driving circuit on the substrate, then the size and production cost decrease, but the complexity of controlling voltage levels during blank periods increases
Solution Approach 1:
The gate driving device performs self-diagnosis through the integrated detection circuit that automatically identifies blank periods and fail modes. The system self-adjusts by stopping gate clock signal generation during these periods without requiring external intervention, thereby managing control complexity while maintaining integration benefits.
3Productivity
If the gate controller continuously outputs gate clock signals, then productivity is maintained, but display defects occur due to unintended voltage applications during blank periods
Solution Approach 1:
The detection circuit provides feedback about the operational state (active period vs. blank period) to the gate controller. Based on this feedback, the gate controller dynamically adjusts gate clock signal generation, stopping during blank periods to prevent display defects while resuming during active periods to maintain productivity.
Data Source
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AI summary
A gate driving device of a display device may include a voltage generator, a gate controller and a gate driver. The voltage generator may generate a gate driving voltage that varies between a gate-on voltage and a gate-off voltage. The gate controller may generate gate clock signals based on the gate driving voltage and gate control signals. The gate driver may generate a gate signal based on the gate clock signals. The gate control signals may include a first control signal and clock control signals, each varying between a high level and a low level. The gate controller may output the gate clock signals having a voltage level of the gate-off voltage when the first control signal and the clock control signals are each provided to the gate controller at the low level, thereby avoiding a display defect due to voltage ramping that may otherwise occur.